SU765879A1 - Shifting device - Google Patents

Description

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The invention relates to computing and discrete automation and can be used in the construction of digital equipment with increased reliability.

Known reserved shift register containing reserved registers and elements And 1.

The disadvantage of the device is that with some failures of more than one element there is a complete violation of the operation of the register.

The closest in technical essence to the proposed is a redundant shift register containing redundant registers, AND elements and OR 2 elements.

In this register, the input information is independently supplied to the reserved registers. The operability of the reserved registers is controlled by the control bits of this register, so the presence of correlation links between the bits of the reserved registers in the integrated design allows the use of indirect control. Reserve bits are used to reserve the main bits.

In the event of a malfunction of the reserved register, the readout of information from the trigger of the main bit of this register is excluded and the information of the reserve bits is used. In the control mode, the control triggers of this redundant register are received by a test program, the KQTora represents two signals that set the control triggers, respectively, in "On n" 1. .. The result of the test is regarded as negative if one of the control triggers is not set to state "1.

The reserved shift register is operable in case of failures of the type "false O, i.e., when the required logical units cannot be you (5 are given and zeros are issued instead.

The drawback of the device is the lack of testing of tested triggers for a failure type of false 1, i.e., a failure in which the corresponding logical values can not be issued and units are issued instead.

The purpose of the invention is to increase the reliability of the shift register.

The goal is achieved by the fact that in a shift device containing registers, the first inputs of which are connected, besides the first register, with one of the outputs of the control signal generator, the other inputs of the registers are connected to the output of the first OR element, one of the inputs of which is connected to the input of the device and the input of the first register, the other input of the element OR is connected to another input of the generator of control signals, and the external elements. OR, the outputs of which are connected to one of the inputs of the first elements AND, the third elements OR, one of the inputs of which are connected to the outputs of the first elements AND, the second and third elements AND and the elements cpaBFieHHH, whose inputs are connected to the first outputs of registers, except the first register, the second outputs of the registers are connected to one of the inputs of the second And elements, the other inputs of which are connected to the first outputs of the comparison elements, the second outputs of the comparison elements are connected to other inputs of the first And elements and the first inputs of the third elements And the first outputs of the second elements AND are connected to other inputs of the third elements OR, the outputs of which are connected to the outputs of the device, the second inputs of the third elements AND are connected to the outputs of the first register, the outputs of the third elements AND and the second outputs of the second elements AND are connected to the inputs of the second elements OR,

The drawing shows a functional diagram of the proposed device.

It contains registers 1 i- {4 (only four registers are shown in the drawing), a generator of 2 control signals, the first element OR 3, the second elements OR 4 1-4, the third elements OR 5 i-5, the first elements And b i-6 3, second elements И 7 1-7 3, elements of comparison 8 i-8, third elements И 9 i-9 l triggers 10-13 of the main bits of registers 1 i-1 4, triggers 14-19 of control bits registers 1 i- i 4, triggers 20-25 reserve bits, device input 26, inputs 27 28 i- 284,, 30, -304, 31, -31 4, 32, -32 4, 33 1-33 4, 34 1-34 4, 35 1-35 4, 36 i-36 4, 37 i37 4, 38 1-38 4, 39 1-39 4 registers, outputs 40-43 devices.

The device works as follows.

Input information is fed independently to device registers i-i 4. For the storage and issuance of information in the registers 1-1-14, the Sh-13 triggers of the main bits are used, as well as the triggers of the 20-25 reserve bits. Triggers 14-19 are used for test control. The operability of the fourth (senior) bit is controlled by three triggers 14–16, the third bit is controlled by two triggers 17–19, the second bit is controlled by one trigger 19, and the first radar is not monitored. The presence of correlation links between the bits of the i-14 registers in the integrated design allows indirect control. The number of control triggers for each bit is a multiple of the weight of the bit. For reservation of the main bits is used by the backup bits. The trigger of the main fourth (senior bit) is reserved by three triggers 20-

22, the trigger of the third bit is two triggers 23 and 24, and the trigger of the second bit is. one trigger 25, the first trigger is not reserved.

The shear device operates as follows.

In the recording mode, information is fed into input 26 independently in each register I -1 4 at their inputs 304, 33 g, 36 o, and 27, to break the shift circuit from the senior to the low-order bit at inputs 29 4, 32 g, 35

38 1 the inhibit potential is applied, and the inputs allowing 29, -29з, 32, -32л 324, 35 ,, 35s, 354, 38 2 and 38 4 are applied to allow information to be shifted. Closed pulses are applied to pins 39, -394.

In the control mode, the test-program for checking the correctness of the registers 1, -1 4 from the first output of the generator 2, the pulse is fed to the inputs 31 4, 34 4 34 h, 37 -37 4 and sets the triggers 14-19 of the control bits to zero. From the second output of the generator 2, a pulse is applied to the inputs 33 4, 36 4,

363 directly and through the element OR 3 - to the inputs 30 4, 33з, 37о. The second impulse from generator 2 sets the triggers 14–-19 of the control bits to “1. The third pulse from the first output of the generator 2 is fed to the input pins 31 4, 34 C, 37 -

374 and sets the triggers 14-19 in “O. Using such a sequence of pulses, transitions of control triggers from the state "O to state" 1 and from the state "L to state" O. are realized. Thus, the proposed device saves ei operability in case of failures “false O and false” 1.

In case of failure of one of the registers 1 | reading out information from the main register trigger of the given register is excluded. In the control, signals from triggers 14-19 are sent to one of the comparison elements 8, -8 $, the information obtained from the control triggers is compared with the information received from generator 2.

In the case of operability from the direct output of the corresponding element of comparison 8, - 8, a resolution is fed to one of the inputs of the corresponding element 7 7-7 3, the second input receives information to be read from one of the trigger 10-13 main bits which is from the output of one of the elements And 7 i-

7 3 through one of the elements 5 i-5 h is fed to the corresponding input of the device.

If the control triggers 14–19 are malfunctioning, a forbidding potential is output from the direct output of one of the comparison elements 8 i-83, and a negative potential, which resolves the potential, goes to one of the inputs of the corresponding element 6i-63 from the inverse output. From the output of the corresponding elements 4 i-4 and the output information from the outputs of elements b 1-6 3 through the corresponding element 5 i-5h is fed to the output of the device. In addition, the resolving potential is fed to one of the inputs of elements 91–9 2, to the other inputs of which information is received from the registers 1 114. Thus, in case of a malfunction of the registrar 1 I-I 4, information of triggers 20–25 of the reserve bits is used.

The technical and economic effect of the present invention is to increase the reliability of the device by indirectly controlling and reserving a multiple of the weight of the discharge. With successive failures of any integrated circuits, information continues to arrive from the shear device without loss of accuracy. Only the failure of the integrated circuit, from which the first main bit is removed, leads to a loss of accuracy, in the case of a four-bit shift register, of the order of 6%. In the event of a malfunction of the integrated circuit from which the first main bit is removed for the N-shift device, the loss of accuracy will be 1r-j 100 (%). Besides,

0

it is possible to control the register without breaking the work cycle.

Claims (2)

Claims A shift device containing registers, the first inputs of which, besides the first register, are connected to one of the outputs of the control signal generator, the other inputs of the registers are connected to the output of the first OR element, one of the inputs of which is connected to the input of the device and to the input of the first register, the other input of the OR element is connected to another input of the generator of the control signals, the second OR elements, whose outputs are connected to one of the inputs of the first AND elements, the third OR elements, some of whose inputs are connected with the outputs of the first And elements, ogly {auschyus that, in order to increase the reliability of the device, the second and third And elements and comparative elements, the inputs of which are connected to the first outputs of registers, are inserted, the cut of the first register, the second outputs of the registers are connected to one of the inputs of the second And elements, the other inputs of which are connected to the first outputs of the comparison elements, the second outputs of the comparison elements are connected to other inputs of the first elements And the first inputs of the third elements And, the first outputs of the second elements Other inputs of the third OR elements whose outputs are connected to the device outputs, second inputs of the third AND elements are connected to the outputs of the first register, outputs of the third elements AND, and second outputs of the main AND elements are connected to the inputs of the second OR elements. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 423175, cl. G ii 19/00, 14.05.77. 2. USSR author's certificate in application number 2361286, cl. G-11 C 19/00, 05/17/76 (prototype). (t. "- TF" r- -   .t.-iT | ("K  ./ --i.i ./765875