SU1387045A1 - Device for checking matrices of cylindrical magnetic film memory with nondestructive readout - Google Patents

Abstract

The invention relates to the field of computer technology, in particular, to devices for monitoring memory matrices on cylindrical magnetic films (CMP), having the property of non-destructive reading. The aim of the invention is to increase the speed of the device. The device contains a control unit 1, an address counter 2, an address decoder 3, a trigger 5, shapers of 6-bit write currents, a trigger 7, an amplitude discrimination discrimination block 8 of a read signal, selectors 9i-9m, a selector selection block 10, a channel selection block 11, counters 12i -12, element I 13, element OR 14. Recording-destruction of information in the device occurs in parallel in the group N of bits of the CMP of the controlled matrix 4, which significantly increases the speed. L zp f-ly, 4 ill.

Description

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The invention relates to computing technology, in particular to devices for monitoring memory matrices on cylindrical magnetic films (CMP), having the property of non-destructive reading.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - functional block selection channel;

for example, the first channel is covered, i.e. trigger 27i is in state "1, and the remaining triggers 27 are in state" O. However, due to the high potential input to input 16, all outputs 19i -19 "are in the open state. In block 10, the inputs 25 are connected to the outputs 22: the selector 9i, since the contacts of the switch 37 are closed with the inputs 25i, the output 35i of the register 35 is the state of the unit, and the contacts are clutches.

in fig. 3 - functional diagrams of the variant 10a 36i are closed, and the keys Zb2-36m of disconnections for the execution of the selectors and the switching unit; in fig. 4 is a functional diagram of an embodiment of the control unit. The device contains (Fig. 1) block 1

With the start of the control, when the trigger 5 is in the state "O", the unit 1 generates a sequence of pulses, control, the counter 2 addresses, a decoder. acting on the counter 2, the decoder 3

3 addresses, controlled matrix 4 of memory per DSP, first trigger 5, shapers 6 write currents, second trigger 7, block 8 of amplitude discrimination of the read signal, bit selectors 9i-9m, block 10 of choice

and shapers b, as a result of which a decoder 3 generates a sequence of address currents arriving simultaneously in several, for example, Q address windings of matrix 4. At the same time, a shape selector, a channel selection block 11, a sequence 12i - 12N of errors, And elements

25

errors, elements of AND 13 and OR NOT 14.

FIG. 1 denotes strobe input 15, selection control input 16, bit inputs 7i -17N, reset inputs 18 and outputs of block 19i -19 and 20 of block 11, information inputs and outputs 211-21 of the device, information inputs and outputs 22i-22m selectors, selection control input 23, switching control input 24, information inputs 25 and outputs 26 of block 10. Block 11 contains (Fig. 2) triggers 27i-27N multiplexers 28i-28N, elements AND 29i-29k and OR-HE 301-- 30N. Each of the selectors 9 -9l contains (Fig. 3) balanced pulse transformers 311-31 N isolators, for example, diodes 31 and-, g 32, l and 322-1-322: m, limiting elements 33 | -33 and 34 ), 342, for example resistors. Block 10 contains (FIG. 3) a circular M-bit shift register 35 with outputs 35) -35p, keys 36i-Zbi, switch 37 and transformer 38.

the decoding write currents of the destruction of zeros, which through block 10 and inputs 22i (Fig. 3) are fed to the input of selector 9. Since all inputs 19i-19ri are in the throughput state coming from the former 6, the discharge currents, depending on which of the two inputs 25 they come in, is distributed either through all the diodes 32i.i-32i.N and the upper (in Fig. 3) windings of transformers 31: -31 N and resistors 33-30 30N, or through diodes 32 1-З22.m, the lower (according to the scheme) windings of transformers 311-31N and the same resistors 33i-33N. In this case, the current-free diodes are locked by a bias voltage UtM through the respective resistors 34i-342. As a result, from the secondary windings of the transformers 311-31 N through the outputs 211-21N to the N elements, the CMP of the matrix 4 receives the alternating discharge currents according to the recording and destruction program generated by unit 1.

40 Thus, QX N bits of matrix 4 are simultaneously affected by a write-destroy zero program, after which unit 1, via element OR-HE 14, trigger 5 is transferred to the state "1, i.e. state of monitoring signals "zeros.

40 Thus, QX N bits of matrix 4 are simultaneously affected by a write-destroy zero program, after which unit 1, via element OR-HE 14, trigger 5 is transferred to the state "1, i.e. state of monitoring signals "zeros.

The control unit 1 contains a clock pulse generator 39, a destructive pulse counter 40, a trigger 41, an OR element 42, a coefficient setting unit 43

recalculation, trigger 44, elements And 45 and 46, 45 recorded bits. Coming to the input OR 47, NOT 48 and AND 49, the decoder 50 and 24 of the block 10 signal from trigger 5 leads to the element OR 51. Switching contacts of the switch 37, and

FIG. 1 and 4 denote the control input 52 — the primary windings of the transformer 38 of the operating mode; the first one is connected to the outputs 22i of that output 53-58, the input 59 of the selector of the selector 9 |. The signal from the trigger 5 to the input of the rational address and the input 60 of the control 50 16 leads in block 11 to select the output by writing the zeros of the block 1 of the control., Post 19i. In selector 9i, a pair of diodes 32i.i and 322.1 is opened by current flowing from the + U source in block 10 through a resistor 33 |. The remaining diode pairs are locked high. The device operates as follows. The potential coming from the non-selected source state triggers the 5 and 7 inputs of 192-19h. The signal from the trigger (Fig. 1), the counters 2 and 12i-12 "are in the state" O at the input 24 low potential also contains the element AND 61, the pulse shaper 62, the elements OR 63 and AND 64.

5 is also fed to the input 52 of block 1, which transfers the counter 2 to the counting mode, in which the decoder 3 forms

The dial inlet is 16 high. In block 11 from 1387045

for example, the first channel is covered, i.e. trigger 27i is in state "1, and the remaining triggers 27 are in state" O. However, due to the high potential input to input 16, all outputs 19i -19 "are in the open state. In block 10, the inputs 25 are connected to the outputs 22: the selector 9i, since the contacts of the switch 37 are closed with the inputs 25i, the output 35i of the register 35 is the state of the unit, and the contacts are clutches.

 cha 3

 cha 36i are closed, and the keys Zb2-36m open

With the beginning of the control, when the trigger 5 is in the state "O", the block 1 produces a sequence of pulses acting on the counter 2, the decoder 3

 acting on the counter 2, the decoder 3

and shapers b, as a result of which a decoder 3 generates a sequence of address currents arriving simultaneously in several, for example, Q address windings of the matrix 4. At the same time, the shaper 6 forms a sequence

6 is formed by the sequence

the decoding write currents of the destruction of zeros, which through block 10 and inputs 22i (Fig. 3) are fed to the input of selector 9. Since all inputs 19i-19ri are in the throughput state coming from the former 6, the discharge currents, depending on of which of the two inputs 25 they come in, they are distributed either through all the diodes 32i.i-32i.N and the upper (in Fig. 3) windings of transformers 31: -31 N and resistors 33-333N, or through diodes 32 1 - Z22.m, lower (according to the scheme) windings of transformers 311-31N and the same resistors 33i-33N. In this case, the current-free diodes are locked by a bias voltage UtM through the respective resistors 34i-342. As a result, from the secondary windings of the transformers 311-31 N through the outputs 211-21N to the N elements, the CMP of the matrix 4 receives the alternating discharge currents according to the recording and destruction program generated by unit 1.

Thus, the QX N bits of the matrix 4 are simultaneously affected by the write-destroy zero program, after which by block 1 through the OR-NOT 14 element the trigger 5 is transferred to the state "1, i.e. state of monitoring signals "zeros.

recorded bits. Coming to the input 24 of the block 10, the signal from the trigger 5 causes the contacts of the switch 37 to switch, and

inputs 192-19n. Trigger Signal

5 is also fed to the input 52 of block 1, which transfers the counter 2 to the counting mode, in which the decoder 3 forms

the address read currents are sequentially in all the indicated Q addresses of the matrix 4. The read signals from the first of the N bits of the matrix 4 through the inputs 211, transformers 311 and 38 arrive at block 8, the input 55 of which receives strobe pulses from block 1. Block 8 outputs at its output a pulse, if the amplitude of the read signal arriving at its inputs 26 from block 10, is less than the set “rejection threshold (discrimination level), and does not generate a signal otherwise.

Thus, block 8 determines the conditionality of each bit of matrix 4. The number of substandard Q bits of the first bit checked is remembered by the counter 12 |, since only the low potential from the output 19i, block 11 arrives at its input, the other counters are 122-12N enters level forbidding account. Following the verification of the last Q-ro bit of the first bit of the matrix 4, arriving at the input 15 from the counter 2, the strobing signal leads to the choice of output 192 in block II, i.e. trigger 27} of block 11 is transferred to the state "O, and trigger 272 is set to one, and the control and registration of the results of monitoring signals of zero signals Q bits of the second bit of matrix 4 occurs similarly, until the end of control of all signals of first zero Q n-ro bit bit When monitoring the signals of this last bit, a high potential is established at the output of 20 bdok 11, and the arrival after the control of the zero signal of the last Q-ro bit of the N-th bit of the signal from the output of counter 2 passes through the elements AND 13 OR-NOT 14 and sets trigger 5 to the zero state, i.e. record, and trigger 7 - in one state. Recording-destruction and control of the signals of the units of the first QXN bits of the first N bits of the matrix 4 occur analogously. After this, the triggers 5 and 7 go to the zero state, which through block 1, counter 2 and decoder 3 leads to the selection of the next, matrix 4 addresses. The whole process of recording and monitoring is repeated for subsequent QXN bits of the first N bits, and so on until all bits of the first N bits of matrix 4 connected to selector 9i are monitored.

In the course of this control, each of the N counters 12i-12N accumulates a number equal to the number of substandard bits detected in the corresponding bit of the matrix 4. At the same time, if this number becomes greater than a predetermined value, from the outputs of the corresponding counters 12i-12N to the corresponding the inputs 17i-17m of the block 11 receive overflow signals (low level), the corresponding of the flip-flops 27i-27c are set to the zero state, and the corresponding of the multiplexers 28i-28N provide an action

five

0

five

0

five

0

five

0

five

Turning off control of these bits during all subsequent control cycles.

At the end of the monitoring of the N first bits from the output 59 of block 1 to the input 23 of block 10, a switching pulse arrives, in register 35 a shift occurs by one bit, as a result of which the contacts of the key Zb | the contacts of the key Zb2 corresponding to the selector 92 are closed, and the same pulse coming from the output 59 of the unit 1 to the input 18 of the unit 11 and the reset inputs of the counters 12i-12N are simultaneously switched to the initial state. Similarly, the process of monitoring the bits of the next N bits of the matrix 4, connected via a switch 212 to the selector 92, begins. This continues until all the bits of the matrix 4 are monitored, after which the device returns to its initial state with a pulse generated at the output 59 of block 1, and the unit signal turns out to be output 35: register 35.

Thus, in the device the recording - destruction of information occurs in parallel in the group N of bits of the controlled matrix 4, which significantly increases the speed.

Claims (2)

1. A device for monitoring memory matrices on cylindrical magnetic films with non-destructive reading of information, comprising an address counter, an address decoder, first and second triggers, an amplitude discrimination discriminator of a read signal, write current drivers and a control unit whose first output is connected to the counter count input addresses Q (where Q is an integer) of the bit outputs of which are connected to the information inputs of the address decoder, the control input of which is connected to the second output of the control unit, the control input and the recording and the third output of which are connected respectively to the (Q + 1) -M bit output of the address counter and the first start inputs of the writing current drivers, the second start inputs of which are connected to the output of the second trigger, and the operating mode input of the control unit is connected to the In my output of the first trigger, the outputs of the address decoder are address outputs of the device, characterized in that, in order to increase the speed of the device, MN-bit selectors are entered into it, where, where P is the number of bits in the controlled matrix memory, selector selector unit, channel selector unit, error counters, OR-NOT element and AND element, the output of which is connected to the first input of the OR-NOT element, the second input and output of which are connected respectively to the fourth output of the control unit and the counting input of the first trigger the direct output of which is connected to the counting input of the second trigger and the switching control input of the selector selection unit, whose information inputs are connected to the outputs of the recording current generators, one of the outputs of the selector selection unit being connected to the information inputs of the amplitude discrimination unit of the read signal, whose gating input connected to the fifth output of the control unit; the other outputs of the selector unit of the selector are connected to the information inputs of the selectors, the selection of which inputs and inputs are set The error counters are connected to the outputs of the first through (Nth channel selection block (Ы + 1)) output of which is connected to the first input of the element I, the second input of which is connected to (Q- | -2) -My the bit output of the address counter and the gating input of the channel selection unit, the selection control input and the bit inputs of which are connected respectively to the inverse output of the first trigger and the outputs of the error counters, the counting inputs of which are connected to the output of the amplitude discrimination unit of the read signal, the selector selection block selection input , reset counters moves tors errors and reset input channel selection unit are connected to a sixth output of the control unit, a selection control input of which is connected to the address output of the second flip-flop, other information the inputs and outputs of the selectors are information inputs and outputs of the device. 2. The device according to claim 1, characterized in that the channel selection block contains triggers, multiplexers, AND elements and OR NOT elements, the outputs of which are the outputs from the first to the Nth block, and the first input of each OR element NOT and the first input of the same multiplexer is connected to the output of the same trigger, the data input of which is connected to the output of the element of the same name AND, the first inputs of elements AND from the first to the Nth and the selection inputs of the multiplexers from the first to the Nth, respectively, are combined and are bit inputs first On the Nth block, the output of each selector, except the last one, is connected to the second inputs of the subsequent AND elements and the selector, the output of the last selector is connected to the second inputs of the first selector and the first AND element, the second inputs of the OR elements are unified and are the selection control input the block discharge, the setup input of the first trigger, and the reset inputs of the remaining triggers are combined and are the reset input of the block, the reset input of the first trigger is connected to the zero potential bus, the trigger synchronization inputs are combined and are Odom gating block, the last output of the multiplexer is an (N + 1) -M output unit. ffff  .. 1 "5. Figo 57 fue / t