SU1183968A1 - Device for checking logical units - Google Patents

Description

The invention relates to digital computing, in particular to automated control systems of logic circuits.

The purpose of the invention is to increase the reliability of control.

The drawing shows a block diagram of a device for controlling logical blocks.

I 10

The device contains a clock pulse generator 1, a shift register 2, a counter 3, a recording unit 4, a switch group 5, two triggers 6 and 7, an OR element 8, a comparison circuit 9, an AND 10 element, a test block 11, a delay element 12, a 'element I13, test register 14, counter 15, OR-NOT 16 element, And 17 element, And 18 element, two display elements 19 and 20, field of the installation set 21, field of forbidden combinations 22, switch 23 of the installation set. The switch group consists of 2 ^P +1 switch „, 25

chalets (n is the number of inputs of the test block), (reset circuits are not shown). The number of digits counter 3.

- equal to n.

In the formation of the hardware model of the tested block 11, all ^ 0, the set of code combinations formed by counter 3 is divided into two subsets: the subset of allowed combinations, in which the installation set, 35, and the subset of forbidden combinations are allocated. In accordance with this partition, switches 5 of the group are set, while the outputs of shift register 2 correspond to the allowed <0 combinations, on which a properly functioning test block

II has a logical response

"1" are connected to the inputs of the circuit OR 8, the outputs of the shift register 2, corresponding to the forbidden combinations, are connected to the inputs of the circuit LINE 16, and the output of the shift register 2, corresponding to the installation set, is connected to the counting input of the counter 15.

The device works as follows.

After the initial installation, when the counter 15 and the counter 3 are set to the zero state, the unit is recorded in the lower bit of the shift register 2, and after the start, the pulses from the clock generator 1 fill the counter 3 and switch the bits of the shift register 2 accordingly. However, until counter 15 is cocked, the code combinations from counter 3 to the test register 14 will not be rewritten, and the code combinations will not be issued to the inputs, respectively; since the input element And 17 receives a logical "O" from the counter 15, resulting in blocking the passage of delayed pulses from the element 12 of the delay at the input of the register entry 14 tests. This continues until the counter corresponding to the installation set is generated on the counter 3. At the same time, the digit of the shift register 2, corresponding to the code of the installation set, is set to logical "1". This signal through 2 ^P + 1 th switch switches 5 groups coax counter 15, after which the pulse from the output of the delay element 12 through the element. And 13 is fed to the input of the record register 14 test. According to this sig3

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The installation set code from the counter 3 is copied to the test register 14 and given to the inputs of the test block 11. According to this code, the test block 11 is set to 5 in the initial state. In the scheme OR 8, a reference response to the code of the installation set is formed, and the unit level from the output of AND 17 permits comparison of this response 10 with the response of the test element 11 in the comparison diagram 9. After this, the monitoring process itself begins. If the allowed code combination was formed on the counter 3, the generated code is entered into the test register 14 and outputted to the inputs of the test unit 11 in the same way as issuing the installation set.

If there is a corresponding closed-20 switch in the field of allowed combinations 21, the element OR 8 receives the logical level "1" from the output of register 2, corresponding to the current code set; if the switch is disconnected from the output of register 2, the logical input "0" is saved at this input of the element OR 8. The response of the tested circuit 11 and the signal from the element OR 8 30

arrive at the circuit 9 comparison. In the case of a non-comparison, the signal from the comparison circuit 9 is fed to the element 10, which ensures the inclusion of the Marriage Indicator 20 and to the registration unit 4, where the number of the input combination is fixed, on which the non-comparison is detected.

If a forbidden code combination was generated on counter 3, then the logical level "1" from the corresponding digit of the shift register 2 through the switch in the field of forbidden combinations 22 enters the input of the OR element - NOT 16. The logical level "0" comes from the output of the OR circuit - NOT 16 enters to the input element And 17, a logical ”0" from the output of which prohibits the comparison and entry of the test code generated in the counter 3 into the register 14. Thus, the prohibited combination is not issued to the block 11 under test.

After a complete enumeration of the combinations, the installation set code will be generated again in the counter 3, and the discharge of the shift register 2 corresponding to the installation set code will be set to a logical "1". This signal through the closed switch of the installation set 23 will cause overflow of the counter 15 and cocking of the trigger 6, which will stop the pulse generator 1 and, if the controlled logic block is healthy, through the element 18 will illuminate the indicator 19 "Goden".

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Claims (1)

A DEVICE FOR THE CONTROL OF LOGICAL BLOCKS containing a clock, a first counter, a shift register, a group of switches, a registration block, a comparison circuit, an OR element, two AND elements, the first trigger, two indication elements, and the output of the clock generator is connected to the counting signal the input of the first counter and the synchronization input of the shift register, the output of the controlled logic block is connected to the first information input of the comparison circuit, the second information input of which is connected to the output of the OR element, output One comparison circuit is connected to the direct input of the first element I, the inverse input of which is connected to the trigger output, the input of the first display element and the inverse input of the second element I, the output of the first element I is connected to the trigger input, the output of the second element I is connected to the input of the second display element, which is different in that it contains a second counter, a second trigger, a delay element to increase the reliability of the control, the third and fourth elements AND, the element OR NOT, the test register, the outputs of the first counter are connected to the information 'inputs of the test register, the outputs of which are connected to the information inputs of the controlled logic block, the input of the element The holder is connected to the output of the clock generator, the output of the delay element is connected to the first input of the third element I, the output of which is connected. with the input of the test register entry, the second input of the third element And is connected to the output of the second element And and the resolution enable of the comparison circuit, the outputs of the shift register from the first to the kth (k is the number of allowed input combinations of the controlled logic block) are connected • ® with the corresponding information inputs of the registration unit and with the first contacts of the corresponding switches of the group, the output of the 1st digit of the shift register (ΐ = 1, .., k) is connected via a 2 + 1-th switch group (η - number of data inputs) are controlled by logic unit counting input of the second counter, the outputs of the shift register with the k + 1 th to ⁿ th 2 are connected to the first contacts of similar groups of switches, the second the contacts of which are connected to the corresponding inputs of the element OR — NOT, the output of which is connected to the first input of the fourth element AND, the second contacts of the switches of the groups 00 00 ¢ 0 Od 00 > 1183968 η,> ι from the first to the K th is connected to sulfur connected to the input of the lock the corresponding inputs of the clock generator element and OR, the overflow output of the second counter is connected to the input of the second trigger, the unit input of which is connected to the output of the first discharge of the second counter, the output of the second trigger input of the second element, And the output of the first discharge of the second counter connected to the second input of the fourth 'element AND.