SU1357939A1 - Timer - Google Patents

Abstract

The invention relates to automation and computer technology and can be used to implement control programs for several objects and technological processes that require different time delays for issuing and removing control signals and commands. A special feature is the (L with SP about 00 with

Description

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Since the timer is equal to one sample of time and does not depend on the number of simultaneously processed intervals, moreover, it is possible to quickly change the duration of the time intervals that are being run when controlling various technological processes. The automatic selection of a free cell simplifies programming due to the possibility of using high level macro commands, since when za-. no information is required on the occupied and free memory locations, and.

one

The invention relates to automation and computer technology and can be used to implement programs for controlling several objects and technological processes that require different time delays and the removal of control and command signals.

The aim of the invention is to expand the functionality by increasing the accuracy of timing of the timing intervals.

Figure 1 shows the timer circuit diagram; Fig. 2 is a block diagram of a memory block; FIG. 3 is a block diagram of the formation of an address; Fig. 4 is a diagram of an information generation unit; Fig. 5 is a block diagram of a write pulse shaping unit; 6 is a control block diagram; figure 7 - diagram of the synchronization unit.

The timer contains a memory block 1, an address generation block 2, an information generation block 3, a recording pulse shaping unit 4, a control block 5, a synchronization block 6, a decoder 7, a multiplexer 8, element 9, element 10, a trunk amplifier 11 , a group of 12 address inputs, a group of 13 time interval inputs, a group of 14 inputs of a timer mode setting, an initial setup input 15, a write enable input 16, a read permission input 17, a group of 18 information outputs, an output 19

in addition, the time of the processor with the timer is reduced, which allows the computer to speed up with temporary commands. The aim of the invention is to enhance the functionality by increasing the accuracy of timing of the time intervals. This goal is achieved by introducing the address generation unit 2, the information generation unit 3, the recording pulse generation unit 4, the synchronization unit 6, the control unit 5, the trunk amplifiers 11, 24, the multiplexer 8. 1 s.p. f-ly, 7 ill.

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five

strobe, timer timer 20 output, trigger output 21, elements 22 and 23, trunk amplifier 24 and outputs 25-27 of synchronization unit 6.

Memory block 1 contains ex nodes: 28 memory, register 29 and delay element 30.

The address generation unit 2 comprises a counter 31, a clock 32, an AND 33 element, a delay element 34, and an OR element 35. The pulse counter 31 from the clock output 27 of the synchronization unit 6 (FIG. 1) entering through the AND 33 element (FIG. 3) at the enable signal from the input of the element OR 10 (FIG. 1) changes the code at its information output . When the counter overflows with pulses, an overflow signal is generated, which is fed to one of the inputs of the element 23, the second input of the setup to the initial state of the control unit 5, and through the delay element 34 (FIG. 3) sets the counter to zero. Switch 32 passes information to the output, which is the address output of block 2, from the output of counter 31 or a group of 12 timer inputs, depending on the signal on the group 14 of the timer mode setting inputs.

The information generation unit 3 comprises an adder 36, a switch 37, an AND 38 element and a register 39.

The write pulse shaping unit 4 comprises a switch 40, a trigger

41, trigger 42, element AND 43, element 44 and NOT element 45.

Control block 5 contains registers 46 and 47, comparison nodes 48 and 49, trigger 50, one-shot 51 and ele-f cops OR 52 and 53.

The synchronization unit 6 comprises a pulse generator 54, a pulse distributor 55, a counter 56, and decoders 57.

The timer works as follows.

After turning on the power to the input 15 of the initial installation, a signal is received, on which triggers 41 and 50,

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On the leading edge of the first such pulse, the buffer register 3 of block 3 records information from a group of 13 inputs, which through a switch 37 enters the information inputs of memory block 1 and a decoder 7. A unit of information words sets the outputs of the decoder 7 to the zero state and the register 46 of control block 5 does not change its state. With a single value of the signal at the input 16, the resolution is written to the input of the commutator from the output of the HE 44 block 4, n

register 46 and the counter 31 is set- f5 its code is a zero signal, write

memory block 1 does not occur. On the falling edge of the positive impulse at the input 16 of the recording resolution, which at the output of block 4 converts into the leading edge of a positive impulse, it records in block 1 of the memory whose address is set at the address input. By sequentially changing the addresses on the group 1 of the time slot inputs and generating the write pulse, the processor drives the memory block 1 to its original state, which corresponds to what is free to receive information.

are in the null state. At the same time, synchronization unit 6 is started, generating clock pulses. On the trailing edge of the pulse from the third output 27 of block 6 is set

in About trigger 42. Trunk usiII

Lines 11 and 24 are in the state.

the third

The processor sets the timer to the direct access mode to the memory unit 1, in which the switch 40 of the unit 4 connects the INPUT signal to the inputs 14. 16 write enable to write enable input of memory block 1, switch 32 of address generation unit 2 connects bus 12 to address block group of block 1, multiplexer 8 connects timer read enable input 17 to block 1 read enable input, connection unit 37 switch 37 The output of the register 39 with the information inputs of the memory 1 is stored. From the processor, to the address inputs 12 is given the starting address of the memory 1, which is fed to its input through the 2.

With a zero signal at the gate input, the decoder 7 outputs signals in accordance with the input information.

The multiplexer 8 passes to the read input of block 1 of the memory signals from the input 17 of the resolution of the NIN or the output of the AND 9 element, depending on the signals of the group of 14 inputs of the timer mode setting.

Trunk amplifiers 11 and 24, with a single signal at the control inputs, pass information from the input to the output, with a zero control signal, the outputs are set to the third state.

On the leading edge of the first clock pulse, the buffer register 39 of block 3 records information from a group of 13 inputs, which through the switch 37 enters the information inputs of memory 1 and the decoder 7. The information word unit sets the outputs of the decoder 7 to the zero state, and register 46 control block 5 does not change its state. With a single value - the signal at the input 16 of the recording resolution, which enters the input of the switch from the output of the element 44 of the block 4, to

5 its code is zero signal, write

0

five

0

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memory block 1 does not occur. On the falling edge of the positive pulse at the input 16 of the recording resolution, which at the output of block 4 is converted into the leading edge of a positive pulse, the cell 1 is written to the memory of the block whose address is set at the address input. By changing sequentially the addresses on the group of 13 time slot inputs and generating a write pulse, the processor sets the memory block 1 to its initial state, which corresponds to the fact that the cells are free to receive information.

In the direct access mode to memory block 1, the processor can write the required information to any cell. In the same mode, the processor

“Has the ability to read information from any cell of memory 1. For this purpose, an address is set up on the group of 13 time slot entries, which is transmitted by block 2 to the address

0 block 1 input. Then a pulse is applied to the read permission input 17, through which information is read from the cell of the memory node 28 at the set address, which is rewritten

5 to the register 29. By a signal from the read enable input 17, the trunk amplifier 11 is set to pass information from the outputs of the memory unit 1, and the read information is fed to a group of 13 inputs for transmission to the processor.

After resetting memory block 1, the timer is set to autonomous mode.

5 In offline mode, the timer can

carry out the following operations: recording the information exposed in a group of 13 inputs (the number of the time relay, the duration of the time interval which

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the relay, the discreteness of the reference of the interval to be set and the sign of cell occupancy) in the free memory of the memory 1, as well as the count of time intervals recorded in the cells of time 1 and the distribution of the numbers of time relay through trunk amplifier 24 to group 18 timer output.

The offline recording is carried out in the following sequence: the search for a free cell in memory block 1; write the required information to this cell.

In order to record the required information by the processor in the autonomous mode of the timer, a group of 14 inputs of the timer mode sets a signal on which the switch 32 of the address generation unit 2 connects the address input of the memory unit 1 to the output of the counter 31, the switch 37 of the information generation unit 3 is connected em information inputs of the memory 1 and the decoder 7 to the output of the register 39, the write enable input of the memory 1, the switch 40 of the block 4 connects to the output of the element And 43, the trigger 50 of the control unit 5 is blocked (it is forbidden to install OUT, in the unit state), the multiplexer 8 connects the read enable input of unit 1 to the output of the AND 22 element.

On the group of 13 inputs, the processor sets the required information and generates a pulse at input 16 of recording resolution acting at the time of the existence of the first clock pulse at output 25 of synchronization unit 6. On the leading edge of this pulse, information from the group of 13 inputs is recorded in the buffer register 39 of the information generation unit 3. At the same time, the write enable pulse arrives at the first write input of block 4 and sets the trigger 41 to one state. The signal 1 from the trigger output 41 through the start output of block 4 is fed to one of the inputs of the elements AND 22 and 23 and through the element OR 10 to the element AND 33 of the block 2, preparing them to start the output signal at the second input. At the control input of the decoder 7 there is a zero signal from the first information code of block 3, which allows the conversion to occur. The code of the discrete value value of the decoder 7 to the first information input of the control unit 5, which is written to the register 46 of the application (appears in one of the bits corresponding to this discreteness of this bit).

The first clock pulse from output 25 through element K 22 and multiplexer 8 reads the information word from the zero address cell of block 1 and rewrites it into the buffer register 29. The information on the cell's busy sign arrives at the information input of the trigger 42 of block 4 and is written on the falling edge of the first clock pulse. in the trigger 42-. Since this cell is free, the trigger 42 is set to one.

Under the action of the second clock pulse from the output 26, the element AND 43 of the block 4, on the two inputs of which there are single signals, passes it through the switch 40 to the input of the recording permission of the memory card 1. The leading edge of this pulse records the word from the information outputs of the information generation unit 3 (from register output 39) to the zero address of memory block 1. The rear of the second clock sets the trigger 41 of block 4 to the zero state and, through its start output, zeroes the counter 31 of the address generation block 2. The zero signal at the output of the start of block 4 (trigger output 41) prohibits the passage of the signal element And 23 and through the element OR 10 prohibits the passage of pulses of the first clock output 25 of block 6. through the elements of And 22 and 33.

The third clock pulse from output 27 sets the trigger 42 of block 4 to the zero state. The recording cycle of the information set by the processor to the free cell is completed.

To write the next word, the pro- processor, which does not change the group of 14 inputs of the timer mode setting, sets the required word to the 13 inputs and at the time of the first clock pulse from output 25 generates a write pulse at input 16 of the write timer, according to which the register 39 of block 3 records this information and through the switch 37 enters the information inputs of memory 1 and decoder 7. At the same time, a write pulse sets the output of block 4 (trigger 41 is cynical) signal 1 allowing the operation of the address generation unit 2 and the AND 22 element.

The third clock to them 27 clears the zero state trigger. Qi information is completed, the first address of the block 1 p

O at the first information exit the required information.

The de information block 3 enables the operation of the decoder 7, from the output of which the discreteness value of the given word is written to the register 46 of the control block 5 (1 appears or is confirmed at the corresponding output of the register 46).

The first clock pulse output

25 through the element And 22 and multiplex. 8 reads from the zero address,

set by block 2, the information word, where O is present, is the sign of the occupation of the given cell. From the first information output of block 1, memory O arrives at informational input of trigger 42 and, on the trailing edge of the first pulse, confirms its zero state.

Second clock pulse output

26 does not pass through the element And 43, block 4 does not produce a recording pulse at its own output.

The third clock pulse output

27 through element 33 of unit 2 enters the counting input of counter 31, increases its contents by one, and the address generation unit 2 sets a new address (in this case, the first) to the address input of memory 1. Next first beat

the pulse from output 25 reads from the first address of the memory block t an information word that contains 1 — a sign of the cell idleness. This single signal from the first information output of block 1 on the trailing edge of the pulse from output 25 is recorded in the trigger 42 of block 4, and when the second clock pulse from output 26 appears, block 4 generates a signal at its output of the write pulse that sends to the first address of block 1 The memory is recorded from the outputs of block 3.

On the falling edge of the clock pulse from output 26 at the start output of block 4, the signal disappears (flip-flop 41 is set to the zero state) and a pulse is generated at its output

25

thirty

ten

In case in N

recorded zero information by the processor (N + 1 4 impulse formation 15 bathes the signal; the start counter 31 of the block 2 begins to count and yes 27, consequently, the most all addresses, from the impulse with the output information. sa address, and pulse overflow counter.H delay counter 31 y to the initial zero point at output 20, one of the vectors of the displacement goes to the advanced program.

At the end of the operation, the operation mode of Thai 46 of the block 5 control unit of all discretes is stored in block 1 of memory O in the field of the indication k, and in the field of the interval of cells there is an interval of the best code that this relay works

After that, the timer operation countdown time. In group 14, timer mode is set by which the switch connects the outputs to the conventional block input 1 tator 37 block 3 sub adder 36 and elemental inputs of the encoder block 7, the switch connects the output of control block 5 to the lag trigger, multiplexer output element and 22 to

35

40

45

50

55

during the reset, setting the counter 31 of the address generation unit 2 to the zero state.

The third clock pulse from output 27 resets the trigger 42 of block 4 to the zero state. The recording cycle of the new information is completed; the zero and first addresses of memory block 1 are recorded

required information

required information

If in N addresses of block 1

recorded zero information, when the processor writes (N + 1) -ro word block ;: 4 write pulse generates a trigger, according to which the counter 31 of the address shaping block 2 starts counting pulses from output 27, thereby changing all addresses, of which every- home impulse output 26 will read the information. Since O is always present at the first information output of block 1, block 4 does not generate write and reset address pulses, and counter 31 causes an overflow pulse. Through the delay element 34, the counter 31 is reset to its original zero state. The output signal 20, which is one of the interrupt vectors, the processor goes to the execution of the corresponding program.

At the end of the write operation in the offline mode of the timer, the register 46 of the control unit 5 records all discrete values that are stored in memory block 1, containing O in the cell busy sign field, and the time interval recorded in the time interval field of these cells in the inverse code that this relay needs to work out.

Thereafter, the timer is closed, the operation of counting predetermined time intervals. In group 14 of the timer mode setting inputs, a signal is set by which the switch 32 of block 2 connects the outputs of counter 31 to the address input of memory block 1, the switch 37 of block 3 connects the outputs of adder 36 and element 38 to the information inputs of memory block 1 decoder 7, switch 40 of block 4 connects the write enable output of control block 5 to the input of write block of memory block 1, the trigger 50 of control block 5 is unlocked, multiplexer 8 connects the output of AND 22 element to allow

No reading of memory block 1. At this point in time at all outputs of the unit.

4 of the recording pulse is set to O, at the output of the start block

5controls (trigger output 50 is signal O, there are no pulses at the output of element And 22, there are no pulses at the counting input of counter 31, the address of the block 1 of memory Q contains the code of the zero address.

The synchronization unit 6 cyclically generates signals corresponding to the current time resolution, which, from its sampling output, are recorded.

are in register 47 of control block 5. Element 48 comparison bitwise compares discrete discreteness

(information of the register 46) with the current (information of the register 47). When one or several bits coincide, the comparison node 18 generates a signal indicating that at block 1 of memory there is at least one word in which the recorded interval of time must be counted with the current discreteness, and which sets the trigger 50 in one state.

A single signal from the trigger output of the control unit control unit 5 (trigger output

50 arrives at the timer start output 21 and through the element OR 10 at one of the inputs of elements AND 22 and 33. The one mode 51 produces a pulse by a single trigger signal 50 and through the element OR 52 it sets all the bits of the register 46 to O. On the first clock the pulse from output 25, which enters through element 40 and 22 and multiplexer 8 to the input of the read resolution of memory 1, reads the information word from the zero address cell, which is

goes to the first and second information; 5 t input of the recording unit resolution 1 and the inputs of the information generation unit 3 to the address set on the address

matsii. 1 at startup output 21 indicates that the timer is performing a counting operation and recording by the processor is not resolved.

The time interval length code enters the adder 36, which increases it by one and transmits to the inputs of the element 38 and the corresponding bits of the first input of the switch 40. If O is at the output of the adder 36, then the first information output of the block 3 (output

50

55

the inputs of memory block 1, a new information word is written from the outputs of block 3.

On the third clock pulse from output 27, the counter 31 of the address generation unit 2 increases its state by one; and through the switch 32 transmits a signal to the address inputs of the memory 1.

The next pulse from the output 25 through the element And 22 and the multiplexer 8 reads the information word and the measurement at the newly established address

five

ABOUT

0

five

element 38) is set to O, which indicates that the interval has not yet been worked out. In the event that 1 is present at all bits of the adder 36, the AND 38 element generates 1, which is fed through the switch 37 to the first information output.

When the signal at the gate input of the decoder 7 is equal to zero (the case when the time has not worked), the decoder 7 passes the positional discreteness code (one in the bit that corresponds to the specified discreteness) to the input of the register 46 and one of the inputs of the node 48 of the block comparison 5 controls The register 46 records the discreteness code of the word, and the node 48 compares the values of the current discreteness at the output of the register 47 and the discreteness of the given word at the first information input of the control unit 5.

The bullet signal from the write output of block 5 is fed to the second input of the write 4 of the block 4 (to the third input of the switch 40) and through it to the write enable of the block 1 of the memory. The recording of the information word from the inputs of the information generation unit 3 does not occur, and the information in this cell of the memory unit 1 does not change.

If the unit on the first information input of control block 5 in the bit corresponding to the discreteness value of the read word in the same register bit register 47 corresponds to 1, the comparison node 48 generates a single signal to the write output of the control block 5. This single signal through block 4 of the formation of a pulse write access 0

five

the inputs of memory block 1, a new information word is written from the outputs of block 3.

On the third clock pulse from output 27, the counter 31 of the address generation unit 2 increases its state by one; and through the switch 32 transmits a signal to the address inputs of the memory 1.

The next pulse from output 25 through element 22 and multiplexer 8 reads the information word to the newly assigned address and modifies it, if necessary, as described.

The address generation unit 2 periodically, by the exit clock 27, increases the address of the memory block 1, from which information is read by the exit clock 25, and depending on the required time resolution in the given word and the current discreteness, the control unit 5 (comparison node 48) generates a resolution pulse writing new information to memory block 1 at the current address, if O is present, the first information output of block 3 from the output of decoder 7 to the register 46 of the control unit 5 is written down the discreteness value of the given word. When the SRI of the counter 31 of the address generation block 2 overflows, the pulse from the address overflow output through the second input of the initial setup sets the block 5 to its initial state, resets the register 47 and trigger 50 to the zero state, thereby prohibiting the pulse from output 27 to the count input the counter 31 of the address generation unit 2 and the pulse from the output 25 to the read enable input of the memory 1 unit. At the same time, through the overflow pulse delay element 34, the counter 31 is reset to the zero state.

Thus, by the time the counter overflows, after polling all the addresses of the cells of memory 1 in the register 46 of control 5, the values of the samples are recorded, with which each time interval (not processed by this time) recorded in memory 1 of the memory should be processed The register 47 is set to the zero state and is ready to receive signals from the outputs of the synchronization unit 6.

When working off the time interval by one of the time relays in an information word read from a specific cell of memory 1, the time interval in all bits except the younger one contains 1. The adder 36 of block 3 increases the code by one and at its output in all bits dah, there are 1 that arrive at the input of the AND 38 element. 1 from the output of the AND 38 element through the switch 37 enters the control input of the decoder 7 and sets it to

the output is all O (i.e., the contents of the register 46 of block 5 does not change), and at one of the inputs of the element AND 9, at the second input of which there is 1 from the first information output of memory 1 (a sign of cell occupancy).

Element 9 of the signal 1, arriving at the gate 19 of the timer and the control input of the main amplifier 24, which passes from the third information output of memory 1 the code of the number of time relay on the 18 information outputs of the timer. The cell from which the time relay was considered was recorded from the outputs of block 3, i.e. a sign that the cell is free and you can write the following information into it (new time relay).

The operation of recording information by the processor into the timer memory block 1 in an autonomous mode is performed at those times when O is present at the timer start output 21, i.e. when there is no comparison of the bits of registers 46 and 47 of control block 5. This allows you to quickly enter the parameters of the new time relays instead of the non-interrupted time counting operations that are in block 1 of the memory.

Claims (2)

1. A timer containing a memory block, a decoder and an AND element, characterized in that, in order to expand the functionality by increasing the accuracy of timing of time intervals, an address generation unit, an information generation unit, a recording pulse shaping unit, a synchronization unit, a control unit, two trunk amplifiers and a multiplexer, the first output of the memory unit being connected to the enable input of the operation of the write pulse shaping unit, with the first input of the first element and with the first information the first input of the first trunk amplifier, the first group of outputs of the memory unit is connected to the first group of information inputs of the first main amplifier and the first group of information HHix inputs of the information generation unit, the second group of outputs of the memory unit is connected to the second group of information inputs of the first main amplifier, and the second group information inputs of the information shaping unit and with a group of information inputs of the second trunk amplifier, whose output group is an info group the mains outputs of the timers, the output of the first element I is connected to the control htHM input of the second main at the silitel and is the gate output; imer, the first output of the information generating unit is connected to the strobe input of the decoder, and the second byte of the first element AND - with the informational input of the memory block, the first 20 dinen with the second permission input for The group of information outputs of the information generating unit is connected to the group of information inputs of the decoder and the first group of information inputs of the memory block, the second group of information outputs of the information forming unit is connected to the second group of information inputs of the memory block, the group of outputs of the first main amplifier is connected to the third group of information the inputs of the information generation unit and is a group of time-interval inputs-outputs of the timer, the write enable input of the timer is connected with the recording resolution input of the information shaping unit and with the first recording resolution input of the pulse shaping unit, recording, a group of inputs of the timer mode setting is connected to the group of control inputs of the shaping unit and recording pulses, with the group of control inputs of the Address generation unit, 1x inputs the control unit, with the control group, the 45th is the output of the timer occupancy, the inputs of the information generation unit of the information form output unit In addition, with the control unit of the multiplexer inputs, the output of which is connected to the read input of the memory unit, the timer enable input is connected to the control input of the first main amplifier and the first information input of the multiplexer, the second information input of which is connected to the output of the second element I, the write enable output of the write pulse shaping unit is connected to the write enable input of the memory unit, the address group 50 55 The write pulse is connected to the information input of the address generation unit, the control block contains a trigger, one-shot, two OR elements, two registers, two comparison blocks, the control section x inputs of the control unit are connected to the input group of the first IZH element, the first input of which is connected with the first input of the second e.pement OR is the first input of the initial installation of the control unit, the second input of the initial setting of which the inputs of which are connected to the group of outputs of the address generation unit, the group of information inputs of which is a group of address inputs of the timer, the input of the initial installation of the timer is connected to the input of the initial installation of the block of formation of the address, with the input of the initial installation of the block of formation of the recording pulse , the start input of the address generation unit is connected to the output of the OR element and to the first input of the second element AND, the output of the address generation unit is connected to the first input t of the second element And the second input of the initial installation of the control unit, the first output of which is five five 0 writing the pulse shaping unit, the second output of the control unit is connected to the first input of the OR element and is the timer flag output, the decoder group of outputs is connected to the control inputs group of the control unit, the clock inputs group of which is connected to the first output block of the synchronization unit, the second output the group of which is connected to the first clock input of the recording pulse-shaping unit, with the second input of the second element I, the second output of the second group of the synchronization block is connected to the second clock input pulse generating unit, recording the second group third output synchronization unit connected to the clock input of the address generating unit and the third clock pulse generating unit vhodom-, recording start output of which is connected to the second input of the FPI element and a second input of the third AND gate, the output of which 0 five The write pulse is connected to the information input of the address generation unit, the control block contains a trigger, one-shot, two OR elements, two registers, two comparison blocks, a group of y-guides x inputs of the control unit is connected to a group of inputs of the first ILI element, the first input of which is connected to and the first input of the second e.pement OR is the first input of the initial installation of the control unit, the second input of the initial installation of which oeflMffeH with the second input of the first element OR and with the input of the recording resolution of the first register, the group of information inputs of which is. the group of clock inputs of the control unit, the group of outputs of the first register is connected to the first group of inputs of the first comparison unit and the first group of inputs of the second comparison unit, the second group of inputs of which is connected to the output group of the second register, the write enable input of which is connected to the output of the second element OR, group address inputs of the control unit is connected to a group The information inputs of the second register and with the second group of inputs of the first comparison unit, the equality output of the first comparison unit is the second output of the control unit, the equality output of the second comparison unit is connected to the single trigger input, the output of which is connected to the input of the single-vibration device, the output of which is connected to the second the input of the second element OR, the address generation unit contains the counter, the element AND, the element OR, the delay element and the switch, with the clock input of the formation unit connected to the first input of the element AND, second The input of which is the start input of the address generation unit, the output of the AND element is connected to the synchronous input of the counter, the counting input of which is the information input of the address generation unit, the output group of the counter bits of the counter is connected to the first group of information inputs of the switch, the second group of inputs of which the group of address inputs of the address generation unit, the group of control inputs of the address generation unit is connected to the group of control inputs of the switch, the output group of which is an inf group The output outputs of the address forming unit, the initial setup input of the block is connected to the first input of the OR element, the second input of which is connected to the output of the delay element, the output of the OR element is connected to the reset input of the counter, the overflow output of which is connected to the input of the delay element and the information generation unit contains a register, an AND element, an adder and a switch, with the write enable input of the The information is connected to the register recording resolution input, the first group of information inputs of the information generation unit is connected to the group of inputs of the adder and the first group of information inputs of the switch, the second group of information inputs of the information generation unit connected to the second group of information inputs of the switch; outputs of the adder are connected to the corresponding inputs of the AND elements and to the third group of information inputs of the switch; output element.and I connected to the information input of the switch; the third group of information inputs of the information generation unit are connected to the group of information inputs the register, the group of outputs of the register is connected to the fourth group of information inputs of the switch, the output of the switch is the first output of the information generation unit, the first and second group of outputs of the switch are respectively the first and second groups of information generation outputs, the input of the adder is connected to the potential potential bus the timer, the control inputs of the switch are connected to the group of control inputs of the information generation unit. 2. Timer pop, 1, which is also distinguished by the fact that the recording pulse generation unit contains two triggers, the OR element, the NOT element, the switch, and the input of the initial installation of the block is connected to the first the input element RSHI, the first input the group of control inputs of the block is connected to the second input of the OR element, the inputs from the second to the nth group of the control inputs of the block are connected to the group of control inputs of the switch, the block write enable input is connected to the input of the element and to the single input of the first trigger, the zero input of which is connected to the output OR, the output of the element is NOT connected to the first information input of the switch, the second information input of which is connected to the output of the AND element and to the third input of the element OR, the output of the first trigger is connected to the first input of the element I, and is the block start output; the first clock input of the block is connected to the synchronous input of the second trigger, the second the clock input of the block is connected to the second bi input of the AND element, the third clock-Vie input of the block is connected to the zero input of the second trigger, whose information input is the output of the block operation resolution, the output of the second trigger is connected to the third input of the AND element, the switch output is the output enable the recording of the block, the third information input of the switch is the second input of the block write expansion. srig.2 15 fig.Z 74fi sixteen 13 39 J7 Srig. 25 26 21 Compiled by N, Toropova Editor O. Yurkovetska Tehred A. Kravchuk Proofreader M. Maksimishinets Order 5999/49 Circulation 671 VNIIGSh of the USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production printing enterprise, Uzhgorod, st. Project, 4 (ig.6 fig l Subscription