SU1336003A1 - Program interruption device - Google Patents

Abstract

The invention relates to computing and can be used in monitoring and control systems to interrupt the main program sequence. The purpose of the invention is to expand the field of application of the device by fixing the masked requests and serving the requests for a limited period of time. The device contains an interrupt register, two mask registers, an encoder, two groups of AND elements, an OR element, a control trigger, three groups of AND-NOT elements, an auxiliary register, a group of OR elements, a group of delay elements, a group of NOT elements, an OR-NOT element, two an AND element, a delay element and a group of consecutive registers, each successive register contains a group of triggers, a group of NAND elements, a group of delay elements. Requests to the device are made based on the state of the first register of masks and are accumulated in successive registers. A request to service any request may be temporarily blocked by the second mask register. Depending on the mode of operation, all unmasked requests can be served either in accordance with their priority, or during the guaranteed time interval. 1 hp f-ly, 3 ill. (L oo with O5 OO

Description

The invention relates to computing and can be used in monitoring and control systems to interrupt the main program sequence.

The purpose of the invention is to expand the field of application of the device by fixing the masked requests and serving the requests for a limited period of time.

FIG. 1 is a functional block diagram of an apparatus for interrupting programs; in fig. 2 - sequential register is functional; in fig. 3 shows timing diagrams of the signals of the Interrupt Request, the Read and the Interrupt Provision (diagrams a, b and c, respectively).

The device contains the first 1 and second 2 mask registers of the group of consecutive registers 3, the group of elements AND-NOT 4, the group of elements AND 5, the register 6 of interrupts, the group of elements 7 delay, the group of elements AND-NOT 8, the group of elements AND 9, the group of elements NOT 10, group of elements AND-NOT 11, auxiliary register 12, group of elements OR 13, encoder 14, elements OR 15, AND 16 and 17 and NOT 18, delay element 19, control trigger 20, element OR-NOT 21, information group 22 device inputs, the first 23 and second 24 device recording inputs, the group of request inputs 25 mouth oystva, group of information outputs of devices 26, 27. The output "requirement interrupting device, input 28" Presentation of an interrupt apparatus, input 29 "Reading devices, inputs guaranteed access 30 and service 31 query term devices.

The serial register contains the group of triggers 32, the group of elements AND 33, the group of elements 34 of delay, the group of elements AND-NOT 35, the information input 36 of the serial register, the output 37 of the sequential register, the input 38 of the mode of the serial register.

The device works in the following way.

Before starting, all triggers of consecutive registers and bits of the interrupt register are set to zero (setting chains to zero are not shown). Registers 1 and 2 of the masks are recorded accordingly, and the information, the unit state of any bit of register 1 of the mask prohibits the passage of the corresponding request to the output of the device, while the corresponding requests are accumulated and will be served after unmasking yes register 1 mask. The unit state of any bit of register 2 masks prohibits the passage of requests for device input even after unmasking this bit

ten

15

20

25

thirty

35

40

45

50

55

previously received requests will not be serviced.

The interrupt request arrives at the corresponding input 25 with a high potential and (if the mask in this register register 2 is 0), the output of the corresponding AND-NOT 4 element is zero and the first trigger 32 of the corresponding sequential register 3 is set to one. After the removal of the signal of the given request, a unit appears at the output of the NAND 4 element and at the output of the first element I 33 of the sequential register a single signal is formed, the leading edge of which sets the second trigger 32 of the sequential register to the 1 state.

The occurrence of a unit at the direct output of the second trigger 32 of the sequential register causes the appearance of a single signal at the output of the second element And 33 of the sequential register, which causes the second trigger 32 of the sequential register to be set to the unit. In addition, a single signal at the forward output of the second flip-flop 32 of the sequential register causes the appearance of a zero at the output of the first AND-NO element 35 of the sequential register, which sets to zero the first flip-flop 32 of the sequential register. The process is then repeated and the request is written to the corresponding register register 6 of the interrupts. If the second request for the same input of the device comes before the first request is served, it will be recorded in the last trigger 32 of register 3, the third request in the penultimate trigger 32, and so on.

If this request is not masked (zero is stored in the corresponding mask register register 1), a single signal appears at the output of the corresponding element AND 9, which, through the elements OR 15 and AND 17, causes the signal "Interruption request."

Consider the operation of the device in the service mode of urgent requests when the control trigger 20 is pre-set to one.

In this mode, after the device issues a signal "Interruption request, requests on other channels continue to enter the interrupt register 6.

In response to the signal, the Computer Interrupt Requirement sequentially exposes the Read and Provide Interrupt signals, which are received respectively at the inputs 29 and 28 of the device. The occurrence of the read signal causes the appearance of a zero at the output of the OR-NO 21 element, which prohibits further passage of requests to the interrupt register 6 in order to prevent a possible change of the interrupt code on the group of outputs 26 of the device at the time of issue.

The appearance of the signal "Provision of an interrupt at the input 28 of the device through the element HE 18 and the element AND 17 causes the output of the signal 27 Demand Interrupt from the device 27 to be removed. In addition, the occurrence of a single signal. The provision of an interrupt at the corresponding inputs of the elements of the AND-NO 11 group causes the appearance of a zero at the output of that of the elements of the IS-NO 11 group, which corresponds to the highest priority request from the number of interrupts stored in register b. A zero signal from the output of the NANDI element 11 causes the corresponding bit of the auxiliary register 12 to be set to a unit and the interrupt code to appear on the information output group 26 of the device.

The control computer, having received the interrupt code, removes the read signal and then the interrupt grant signal.

The appearance of a zero signal at the device input 28 "Providing an interrupt causes the interrupt code to be removed from the group of information outputs 26 of the device and causes the appearance of a zero signal at the output of the corresponding element OR 13 of the group.

A zero signal from the output of an element OR 13 of a group causes a reset of the corresponding register register 6 of interrupts and ensures the appearance of a zero signal at the output of the corresponding element AND 5 of the group, thereby preparing the corresponding register register 6 of interruptions to receive the next request.

The zero signal from the direct output of the serviced bit of the register 6 interrupts causes the corresponding bit of the auxiliary register 12 to be set to zero, which leads to the appearance of a unit at the output of the corresponding element OR 13 of the group. If there are unserved requests in this sequential register 3, a single signal appears at the output of the corresponding element AND 5 of the group, the leading edge of which sets the corresponding register bit 6 of the interrupts.

The transition to the unit of the register register 6 interrupts causes the appearance of a zero signal at the output of the corresponding element of the IS-NO 8 group, which sets to zero the last trigger 32 of the sequential register and causes the appearance of a zero at the output of the last element AND 33 of the sequential register, thus preparing The last trigger 32 registers 3 to write the next request. After a group IS-NE element 8 transitions to the one state (the pulse duration is determined by the parameters of the delay element 7), the last trigger 32 of the sequential register goes to the one state (if there is one in the penultimate trigger 32 of the register 3) and at the output of the last I- element NOT 35 register 3 appears zero. The process is then repeated in the same way. As a result, all requests written to register 3 are shifted to the right.

Writing to the other registers 3 is similar. As a result, in register 6, the interrupts are in cc units n at output 27

The Q device again receives the interrupt request signal. Delay element 19 serves to prevent the "Interrupt request" signal from being issued before the bit of the interrupt register register 6 is set to zero, corresponding to the serviced demand.

In the new service cycle, at the information outputs 26 of the device, an interrupt code will be issued, corresponding to the most priority request that has been detected at the input of the interrupt register 6 before receiving a new read signal.

Thus, in the service mode of urgent requests, in each service cycle, the highest priority request interrupt code will be issued, i.e.

5, requests with lower priority will not be serviced until all requests with higher priority have been served.

In the mode of providing guaranteed access control trigger 20

0 is set to zero. The operation of the device until the recording of information in the register 6 interrupts occurs similarly to the operation of the device in the mode of guaranteed access. When an unmasked request appears in the interrupt register at the output of the AND 16 element, a unit appears that causes the appearance of a zero at the output of the OR-NOT 21 element. A zero signal from the output of the OR-NOT 21 element locks the group of AND 5 elements prohibiting a further entry in the register of 6 interrupts.

0 After servicing this request, the corresponding register bit 6 of the interrupts is zeroed, the outputs of the OR 15 and AND 16 elements appear zero, the output of the OR-NE 21 element is the unit that allows writing to the interrupt register 6. In this case, those bits in the register 6 of the interrupts, in the channels of which there are interrupt requests, will go to the unit state.

If among the received requests there are not Q masked ones, units appear at the outputs of the OR 15 and AND 16 elements, the output of the OR-NOT element 21 is zero, and further writing to the interrupt register 6 will be prohibited until the last unmasked 5 request in register 6 interrupts. After that, the cycle is repeated and a new series of requests is stored in the interrupt register 6.

Thus, when the device operates in the guaranteed access mode, any unguarded request after a certain time will cause the programs to be interrupted regardless of the flow rate of applications with a higher priority.

Claims (2)

Claims 1. Device for interrupting programs. By the names of the second-group IS-NOT elements whose outputs are connected to the mode inputs of the corresponding successive registers, the first inputs of the IS-NOT elements of the second group are connected to the direct outputs of the corresponding interrupt register bits and to the zero inputs of the corresponding bits of the auxiliary register the first group is connected to the first input corresponding to the interrupt register, the register element of the third element AND IS, the third group, the output of the mask, an encoder, two groups of elements of the / th element AND of the first group (t 1,), AND, OR element, AND element, control trigger, where the group of information inputs of the first mask register is a group of information inputs of the device, the direct outputs of the bits of the interrupt register are connected to the first inputs of the corresponding AND elements of the first group, the outlets of the identifier are the group of information outputs of the device, inverse outputs of the bits of the first register of the mask 20 Home "Providing the interruption of the device is connected to the second inputs of the I elements, the outputs of the elements AND-NAND of the third first group, the outputs of the elements And the first ntov 15 L - the number of request inputs of the device) is connected to the (/ + 1) th input of the NOT element of the group, the output of which is connected to the () th inputs of the AND-NE elements of the third group with (i- | -l) o through NK, (/ +1) inputs / -h. {1, Л) elements of the third group AND-NOT are connected to the first inputs of the OR elements of the group, to the input of the NOT element, to the first input of the OR-NOT element and from the upper group to the corresponding inputs of the encoder and to the single inputs of the corresponding bits of the auxiliary register, inverse the outputs of which are connected to the second inputs of the corresponding OR elements, the output of the OR element is connected to the first input of the second element AND, the second input of the first AND element is connected to the inverse output of the control trigger, whose single input is dinene to the service input of urgent requests of the device, the output of the first element AND is connected to the second input of the element OR NOT, the third input of which is connected to the input "Read device, the output of the element is NOT connected to the second input of the second element AND, and to the input of the delay element whose output is connected with the third input of the second element AND, the output of which is the output of the device interrupt request. 2. The device according to claim 1, characterized in that the serial register contains a group of triggers, a group of elements AND, a group of elements AND-NOT and a group of elements of delay, and the information input of the serial register is connected to the single input of the first trigger FUP-5p and the input of the first element AND of the group, the output of the I-I (, 2, ..., t, t is the number of accumulated requests from one source) of the element I is connected to the clock input of the (/ + 1) th trigger, the direct output of the I-I trigger connected to the second input 25 thirty 35 the groups are connected to the corresponding inputs of the OR element, the output of which is connected to the first input of the first element AND, the zero input of the control trigger is connected to the input of the guaranteed access of the device, characterized in that, in order to expand the scope of application by fixing the masked requests and serving the requests for limited period of time, the second mask register, three groups of NAND elements, auxiliary register, a group of OR elements, a group of delay elements, a group of elements are entered into the device NOT, element OR-NOT, second element AND, element NOT, delay element, group of successive registers, the group of information inputs of the second mask register is connected to the group of information inputs of the first mask register, clock inputs of the first and second mask registers are connected respectively the first and second inputs of the device record; the inverse outputs of the second register of the mask are connected to the first inputs of the corresponding NAND elements of the first group, the second inputs of which are the group of request inputs of the device, input AND-NO elements are connected to the first group of information inputs of respective successive groups of registers, whose outputs are connected to respective first inputs of AND gates the groups are connected to the corresponding inputs of the shifter and to the single inputs of the corresponding bits of the auxiliary register, the inverse outputs of which are connected to the second inputs of the corresponding OR elements, the output of the OR element is connected to the first input of the second element AND, the second input of the first element AND is connected to the inverted output of the control trigger , the unit input of which is connected to the service entrance of urgent device requests, the output of the first element AND is connected to the second input of the element OR NOT, the third input of which connected to the input "Reading devices, output element is coupled to the second input of the second AND gate and to an input of a delay element whose output is connected to a third input of the second AND gate, whose output is the output of" requirement for interrupting device. 2. The device according to claim 1, characterized in that the serial register contains a group of triggers, a group of elements AND, a group of elements AND-NOT and a group of elements of delay, and the information input of the serial register is connected to the single input of the first trigger FUP-5p and the input of the first element AND of the group, the output of the I-I (, 2, ..., t, t is the number of accumulated requests from one source) of the element I is connected to the clock input of the (/ + 1) th trigger, the direct output of the I-I trigger connected to the second input the second group, the second inputs of which are the 1st element AND, the direct output (mf 1) of the dinene with the output of the OR-NOT element, the third inputs of the AND elements of the second group are connected to the zero inputs of the corresponding interrupt register bits and to the outputs of the corresponding of the elements of the group merger connected to the output of the sequential register, the inverse output of the C th trigger (K-2, m + 1) through (/ C-1) -th delay element connected to the first input of the (K-1) -th 55 element AND -NON, the second input of which is co-op, a group of inverse outputs of the interrupt register through the corresponding th delay elements connected to a second group vhoschego AND-NO element of the third group, the output of the / th element of the first group and (t 1), the house "Providing ustroy- CTBA interruption, outputs of the AND-NOT-third L - the number of request inputs of the device) is connected to the (/ + 1) th input of the NOT element of the group, the output of which is connected to the () th inputs of the AND-NE elements of the third group with (i- | -l) o through NK, (/ +1) inputs / -h. {1, Л) elements of the third group AND-NOT are connected to the first inputs of the elements of the OR group, to the input of the element NOT, to the first input of the element OR-NOT and to the third element AND-NOT of the third group, the output of the -th element AND of the first group ( t 1,), House "Provision of interrupt devices, outputs of AND-NOT elements of the third the groups are connected to the corresponding inputs of the shifter and to the single inputs of the corresponding bits of the auxiliary register, the inverse outputs of which are connected to the second inputs of the corresponding OR elements, the output of the OR element is connected to the first input of the second element AND, the second input of the first element AND is connected to the inverted output of the control trigger , the unit input of which is connected to the service entrance of urgent device requests, the output of the first element AND is connected to the second input of the element OR NOT, the third input of which connected to the input "Reading devices, output element is coupled to the second input of the second AND gate and to an input of a delay element whose output is connected to a third input of the second AND gate, whose output is the output of" requirement for interrupting device. 2. The device according to claim 1, characterized in that the serial register contains a group of triggers, a group of elements AND, a group of elements AND-NOT and a group of elements of the delay, and the information input of the serial register is connected to the single input of the first trigger of a group and the first element And group, output / -TH (, 2, ..., t, t is the number of accumulated requests from one source) of element And is connected to the clock input of (/ + 1) -th trigger, direct output / -TH trigger connected to the second input 1st element I, direct output (mf 1) -th  1st element I, direct output (mf 1) -th the trigger is connected to the output of the serial register, the inverse output of the / C-th trigger (K-2, m + 1) through (/ C-1) -th delay element connected to the first input (K-1) of the 55th AND-NAND element whose second input is connected to the forward output of the C th trigger, the output of the I th element of the NAND is connected to the second input of the (K-1) th element of the AND, and to zero the input of the K-th trigger, the output of the first ele-element I is connected to the zero input The AND gate is connected to the zero input of the (t + 1) th trigger and is the input of the first trigger, the second input of the (t + 1) th sequential register. gz 30 D / FIG. / 37 Compiled by M. Sorochan Editor P. GereshiTehred I. VeresKorrektor M. Beskid Order 3803/44 Circulation 672 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab., D, 4/5 Production and printing company, Uzhgorod, ul. Project, 4 FIG. 2 fig.Z