SU1378024A1 - Multichannel device for shaping time intervals - Google Patents

Abstract

The invention can be used in the equipment of automated telemechanics and computer technology and serves to expand the functionality of the device in terms of the formation of a fixed sequence of time intervals. The device contains a memory block 1, counters 2 and 8 pulses, trigger 5, element 7, switch 9 and block 12 sync. The introduction of the comparison unit 3, the decoder 4, the switches 10 and 11, and the formation of new functional connections allows comparing the start time values for each time interval with the current time value and then filling in the result of the time determined by the duration of each time interval. 2 Il.

Description

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The invention relates to a pulse technique and can be used in automation equipment, telemechanics and computer technology. The aim of the invention is to extend the functionality in terms of the formation of a fixed sequence of time intervals by comparing the start time value for each time interval with the current time value, followed by filling the result by the time determined by the duration of each time interval.

FIG. 1 shows a block diagram of a multi-channel device for forming time slots in FIG. 2 - timing charts of the synchronization unit.

The multichannel device for forming time slots contains (Fig. 1) memory block 1, pulse counter 2, comparison block 3, decoder 4, trigger 5, output bus 6, AND element 7, counter of impulses 8, switches 9-11, synchronization unit 12, Start bus 13, bus 14 Mode setting, address bus 15, information buses 16, 17, external synchronization bus 18, the bus 13 Start is connected to the first input of the synchronization unit 12, the mode set bus 14 to the second input the input bus 18 external synchronization, the sixth output of the block 12 synchronization connection with the input of the counter 8, the second output with the control and the inputs of the switches 9-11, the first output with the control input of the memory block 1, the third output with the second input of the counter 2, the fourth output with the synchronizing input of the trigger 5, the fifth output with the second input element And 7 and the seventh output with the gate input of the decoder 4, the first output of the counter 8 is connected to the second input of the switch 9, the first input of which is connected to the address bus 15, and the second output to the first input of the comparator 3, the second input of which is connected to the first the output of block 1 and with the first in Odom counter 2, and an output coupled to the data input of flip-flop 5, the second output block of the connections with 1 cos output bus bis trigger input apparatus 1 5 About set input coupled to an output of the decoder 4, an input soe5

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dinene with the output of the first counter 2 and with the input of the switch 11, the output of the trigger 5 is connected to the first inputs of the element 7 and the switch 10. The output of the element 7 and is connected to the third input of the counter 2, the first inputs of the switches 10 and 11 are the input data buses .16 , 17, the output of the switch 9 is connected to the address input of block 1, and the outputs of the switches 10, 11 with the first and second information inputs of block 1.

The device works as follows.

In the initial state, the counters 2 and 8 are zeroed out, and the synchronizing pulses at the output of the synchronization unit 12 are absent. Before the start of work, block 1 records information about each time interval, for which a write flag is placed on mode setting bus 14, and clock synchro pulses are supplied to external clock 18, along which synchronization unit 12 generates recording signals for block 1 on the third output, and on the second - for switches 9-11. Through the switch 9, addresses from the external device are sent to the address inputs of block 1, and information from the external device is sent to the information inputs of block 1 through the switches 10, 11. The tenth i-th (... n) time interval is specified by the start time () and duration (), with t (recorded in the 21st cell, in the lower bits (21 + 1) -th cell. In each (21 +1) -and the cell has an additional high-order bit for the start interval, the presence of 1 in which means the presence of the i-ro time interval at the moment, O - the absence of the i-ro time interval.

The operation of the device begins with the arrival of the Start command on block 13 of the synchronization unit 12, according to which the synchronization unit 12 begins to generate clock pulses cyclically.

Each cycle of the synchronization unit 12 contains two phases. In the first phase, information is processed in one time interval, in the second, interaction with external devices.

Sequential selection of information for each time interval is carried out with a period of to using

the lower bits of counter 8, and its high bits are used to count the time from the moment the Start command arrives on bus 13. The number of high bits is determined by the required operating time of the device and the necessary accuracy of forming time intervals. The change in the state of the higher bits of the counter 8 occurs every time after the processing of information over the nth time interval is completed.

The processing of information on the ith time interval in the first phase of the cycle is performed as follows.

At the second output (Fig. 2b) of the synchronization unit 12, a signal is generated that arrives at the switches 9-11 and provides connection to the corresponding inputs of block 1 of the lower bits of the counter 8, the counter 2 and the trigger 5.

The low bits of the counter 8 through the switch 9 are fed to the address inputs of block 1, to the control inputs of which from the third output (FIG. 2 c) of the synchronization block 12 receives a read signal, while from the 21 cells of the block 1 the encoding is read which is compared in block 3 with the higher bits of the counter 8. The result of the comparison is fed to the input D of the trigger 5 and is written into it by the sync pulse produced at the fifth output (Fig. 2e) of the synchronization block 12. After that, at the first output (Fig. 2a) of the synchronization unit 12, a sync pulse +1 is output to the input of the counter 8, and then the code and the indication of the interval start are read from block 1. Code t „; The sync pulse generated at the fourth output (Fig. 2d) of the synchronization unit 12 is recorded in counter 2, and the indication of the start of the interval enters input S of the trigger 5. The trigger 5 can thus be turned on if the code tj ,; coincided with the code of the current time or if the start sign and the terminal 1 is equal to 1 for the processed time interval. Next, at the sixth output (Fig. 2e) of the synchronization unit 12, a synchronous pulse -1 is formed, which through the element 7, if the trigger 5 is turned on, enters the counter 2 and its contents are reduced by 1. If in the counter

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2 turns out to be null coding, then at the output of the decoder 4, a sync pulse generated at the seventh output (Fig. 2g) of the synchronization unit 12, generates a signal that goes to the input R of the flip-flop 5 and sets it to O, which means that the i-ro temporary formation interval.

After that, synchronization unit 12 at the third output generates a recording signal, according to which the contents of counter 2 are rewritten to lower bits, and the contents of trigger 5 to the most significant bit (21 + 1) and cells of block 1.

In the second phase of the cycle, interaction with external devices takes place. At the third output of the synchronization unit 12, a write or read signal is generated in accordance with the selected mode of operation on bus 14, and at the second output, a signal is generated by which the input address buses 15 and information buses 16, 17 are connected through switches 9-11 to the corresponding inputs of the block 1. In the recording mode, you can change the contents of any cell and thus change the value of the start time and duration over any of the time intervals, and you can also start or stop any i-ro time. In the read mode, the value of the 1st time interval on the input address bus 15 sets the address of the (21 + 1) cell and, according to the read signal to the output bus, 6 shows the indication of the start of the 1st time interval. At the end of each cycle, at the first output of the synchronization unit 12, a sync pulse +1 is generated, according to which the lower bits of the counter 8 provide for the selection and processing of information over the (1 + 1) -th time interval.

Claims (1)

Invention Formula A multichannel device for the formation of time intervals, containing a first pulse counter, the first input of which is connected to the output of the element I, a trigger, a synchronization unit, a memory unit, the first switch, the first input of which is the input address bus, the output of the first switch is connected to the first input of the memory block, the first output of which is connected to the second input of the first pulse counter, and the control input of the memory block is connected to the first output of the synchronization block, the second output of which is connected to the control input of the first switch , the third output of the synchronization unit — with the third input of the first pulse counter — the fourth output connected to the gate trigger input, and the fifth output to the first input of the AND element, characterized in that, in order to expand the function capabilities, a comparison unit, a decoder, second and third switches, a second pulse counter, the input of which is connected to the sixth output of the synchronization unit, a first output of the second pulse counter is connected to the second input of the first switch, and a second output to the first input of the comparison unit. , the second input of which is connected to the first output of the memory unit, and the output of the comparison unit - to the informational input of the trigger, the installation input to 1 of which is connected to the second the output of the memory unit and the output bus of the device; the output of the trigger is with the second input of the element I and the second input of the second switch, the first input of which is the first input information bus, the output of the second switch is connected to the second input of the memory block, and the control input is with the second output of the synchronization unit and with the control input of the third switch, the first input of which is the second information bus, the output of the third switch is connected to the third input of the memory block, and the second input is connected to the output of the first impu counter The second input of the decoder is connected to the seventh output of the synchronization unit, the inputs of which are the Start, Task mode and External synchronization buses, respectively.