SU1418726A1 - Multichannel analog information input device - Google Patents

Abstract

The invention relates to computer technology and can be used in information measuring systems and hybrid computer systems for the communication of analog and digital computers. The aim of the invention is to expand the scope by

Description

eliminating redundancy of input information. The multichannel device for inputting analog information contains switches 1 and 6, analog-digital converter 2, digital-analog converter 4, signal increment analysis unit 3, memory blocks 5 and 19, synchronization unit 11, counters 7 and 10, status register 20 , buffer register 24, elements

comparisons 8 and 16, comparator 13, pulse generator 18, triggers 12 and 17, elements AND 9, 21 and 23, elements OR 15, 22, 25 and 26. Compressing data in analog form allows you to eliminate redundant samples in time, and therefore , reduce the time to enter information and increase the bandwidth of the high-frequency channels of the device. 1 hp f-ly, 5 silt „

The invention relates to computing technology and can be used in information measuring systems and in hybrid computer complexes for the communication of analog and digital computers.

The aim of the invention is to expand the scope by eliminating the redundancy of the input information.

formations.

Figure 1 shows the scheme of the multi-channel input device analog information; figure 2 - diagram of the synchronization unit; FIG. 3 is a block diagram analysis of signal increments; Fig. 4 shows a block of the algorithm, explaining the operation of the device in the encoding process; Fig. 5 is a block diagram of the device operation in the process of reading.

The multichannel device for inputting analog information (Fig. 1) contains the first switch 1, the analog-digital converter 2, the increment-signal analysis block 3, the digital-analog converter 4, the first memory block 5, the second switch 6, the first counter 7, the first comparison element 8, first AND 9 element, second counter 10, synchronizer unit 11, first trigger 12, comparator 13s delay element 14, second element OR 15, second comparison element 16, second trigger 17, pulse generator 18, second memory block 1.9 , the state register 20, the second element AND 21, the first element OR 22, T1) this element AND 23, the buffer register 24, the third element OR 25 quarter element OR 26.

with

Q

j 0

5 o.

five

The synchronization unit 11 contains (FIG. 2) the seventh element OR 27, the second distributor 28 pulses, the sixth element OR 29, the fifth element OR 30, the third trigger 31, the first distributor 32 pulses, the fourth element AND 33, the fifth element AND 34 , the sixth element and 35.

The signal increment analysis unit 3 comprises (FIG. 3) an operational amplifier 36, a threshold element 37, an emitter follower 38, a signal level matching unit 39, a memory element 40. I

The device works as follows

Input analog signals through switch 1 are sequentially received in time at the input of analog-digital converter 2 and at the first input of signal increment analysis unit 3, to the second analog input of which through digital-analog converter 4 enters the analog form of the signal over the polled channel received in the previous cycle survey. The signal increment analysis unit performs the function of monitoring the signal change at the input of the polled channel. Since the series-connected operational amplifier 36 and the emitter follower 36 are covered by a deep negative feedback, the signal at the output of the emitter repeater 38 fully corresponds to the signal on the non-inverted input of the operational amplifier 36, respectively, the potentials at the bases of the emitter transistors

3141

Repeater with floating input are equal.

and; UBX + and; ;

uj ue. - and;

where and- “is the voltage on non-invertiOl

the leading input of the operational amplifier Zb;

and,, U, g-, respectively, the voltage of the emitter-base of the upper and lower output transistors of the emitter follower.

The voltages U and U are the setting potentials for the threshold element 37. The dead-circuit diagram of the threshold element consists of resistors, a diode switch and an inverting amplifier. The input of the threshold element 37 is the second analog input of the incremental analysis unit 3. Taking into account the fact that, for a threshold element with a dead zone, the relations

 and

 and

-Si RO - IL

S

where A and B are the width of the dead zone in volts for the voltages at the second analog input of the unit 3 for analyzing the signal increments and, accordingly, for larger and smaller values of Ug. For example, if (Uj) (.Ug.) Is 0.6 V, and R ,, then (A) (B) is 30 mV, i.e. the threshold element with deadband 37 does not respond to the difference in the values of the signals on the first and second analog the inputs of the unit 3 analysis of the signal increments in the range of + 30 mV. This is due to the fact that while the difference of the input signals is small, the current through the resistor R is less than the control current of the diode switch and, therefore, the feedback current that is closed through the diode switch provides a deep negative feedback of the inverting amplifier. the output at its output differs little from the voltage at the potential input of a threshold element with a dead zone. But how

6

only the feedback current due to the increasing imbalance on the analog inputs of the incremental signal analysis block 3 begins to approach and exceed the control current of the diode switch, the feedback of the inverting amplifier of the threshold element 37 is broken, which at a sufficiently high gain factor leads to a sharp increase in voltage at its output, up to the voltage of the power sources "Depending on the algebraic value of the unbalance of the signals, the voltage at the output of the threshold element 37 with a insensitivity is close to the value of the voltage of a positive or negative power source.

Node 39 for matching the signal levels allows to reduce the difference of the output signal of the threshold element 37 to the standard signal of one polarity. The resistor Rj sets the node triggering level, for example, when the analog signal range of the device is +10 V and the inverting supply voltage

the threshold element amplifier with the +15 V deadband the node of the level matching should operate in the range of +10 15 V or 10 - -15 V, the output signal of the node 39 of the matching

signal levels are fed to memory element 40. Writing to the memory element 40 occurs by a signal on the synchronous input of the signal increment analysis unit 3. The output of the memory element 40 is

control output unit 3 analysis of the signal increments.

Thus, the state of the control output of the unit 3 for analyzing the signal increments corresponds to the ratio

analog signals at its first and second analog inputs at the time of arrival of the signal on the synchronous input. If the difference between the analog signals exceeds the permissible level, then

the control output of the signal increment analysis block will be a logical one; otherwise, a logical zero

Output block 3 analysis increments

signal permits (or not permits)

the operation of the second switch and the launch of the analog-digital converter 2. If the difference in the signals of the polled signal is

5U

Currently and at the time of the previous encoding within the tolerance, to analog-to-digital converter 2 does not encode, but the device proceeds to polling the next channel. If the difference in signals exceeds the established tolerance, then analog-to-digital converter 2 coordinates the signal, the result of the coding is recorded in the first memory block 5, where it updates the stored information about the signal on this channel, then in the second the memory unit 19 sequentially records the address of the channel under survey and the result of the channel coding. The external device reads the collected information from the second memory unit 19. Moreover, each data word is accompanied by the address of the channel on which it was received. If there were no changes in the signal from the time of the previous polling cycle, then new data in the second memory block 19 through such channels did not

is recorded I

Such a logic of operation of the multi-channel input device for analog information is provided as follows. The initial setup signal provides reset to the zero state of the buffer register 24, state register 20, through the OR element 26 of the second trigger 17, through the IMM 22 element of the first trigger 12 and through the OR element 27 of the third trigger 31, the output of the first trigger 12 informs the external device about the readiness of the measuring part of the input device analog information. The zero state of the output of the trigger 12 indicates the absence of the data entry process carried out by the measuring part of the device. The output of the second trigger 17 indicates the state of the second memory block 19. A single output of trigger 17 indicates that there is unwritten information in the second memory block 19 after the next polling cycle. The outputs of the flip-flops 12 and 17 in the system can be used as initiators of interrupts or outputs of the status register during asynchronous program exchange.

In the operating state, the multichannel analog information input device is driven by writing to the state register 20 the status word of the device. With the system bus

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data in the state register 20 is recorded unit in the most significant bit, the address of the channel, to which the sources should be polled in the cycle, the address of the first channel of the survey in the cycle. Therefore, the device allows you to set the number of polled ka-. cash in a loop within physically

0 existing channels of the switch 1 analog signals B In the 20 state register, information from the system data bus is recorded on the leading edge of the addressed system sync pulse. Using the cut of the same pulse, the OR register 25 is used to overwrite from the state register 20 into the first counter 7 of the first channel address in 1 click polling. When the output from the first trigger 12 occurs at the moment of parallel recording, the counter 7 is held in parallel recording mode. Thus, the word-state entered in the state 20 register 20 consists of three parts: the most significant bit is the operating state of the measuring part of the device; the group of bits corresponding to the second state register output 20 is the address of the first

3Q channel in the survey cycle; a group of bits corresponding to the third output of the state register 20 — the channel address with the number one more than the address of the last channel in the polling cycle

35 After the state word is written to the state register 20, the most significant bit of the state word from the first output of the register 20 is allowed to start the pulse generator 18 through AND 21

40 system clock pulses that gates the start of the channel polling cycle by the device. Pulses from the generator 18 pulses are received by quarter 33 and five to 34 elements AND blocks

45 11, but, since the third trigger 31 is preset to the zero state5 pulses from the generator 18 pulses arrive only at the output of the fourth element AND 33 and, therefore, arrive at the input of the first distributor 32 pulses. The signal from the first output of the first distributor 32 pulses unit 11 enters the synchronous input of switch 1 and

155 through the second element OR 15 to the synchronous input of the first memory block 5. It should be noted that since before this, the address of the first channel in the cycle is written in parallel in the first counter 7

11 1

the second element OR 15 (. on the front) records data from the output of the analog-digital converter 2 to the memory cell of the first memory block 5, which was addressed to the first counter 7 from the output of the first counter. In addition, the tonal signal The end of the coding finally unlocks the fifth element AND 34 and the clock pulses; the pulses begin to arrive at the input of the second pulse distributor 28. It should be noted that the second switch 6 is addressed from the third output of the second pulse distributor 28. Therefore, after the input potential from the control output of the unit 3 for analyzing the signal increments and the presence of a zero potential at the input of the second switch 6, its output is connected to the output, to which the output of the first counter 7 is connected, i.e. At the output of the second switch 6, the address of the polling channel is currently displayed. A pulse from the first output of the second pulse distributor 28 through the fifth element OR 30 into the second memory block 19 records the address of the polled channel. The cell address of the memory block 19 is set from the output of the second counter 10. If this is the first entry in the polling cycle after the initial installation, the cell address will be zero. The signal from the second output of the second distributor 28 pulses through the sixth And 29 element is at the counting input of the second counter 10, its content is incremented by one; in the second memory block 19, the next cell is already addressed. The signal from the third output of the second pulse distributor 28 changes the addressing of the second switch 6, which now switches to the data bus from the output of the analog-digital converter 2. In addition, a clock signal is input through the fifth element OR 30 to the input of the second memory block 19, which leads to recording data from the analog-digital converter 2 to the second memory block 19 at a one more address than the previously recorded address of the polled channel. By signaling from the fourth output of the second distributor 28 pulses through the sixth element OR 29, the contents of counter 10 are increased by one, which is preparation

872612

addresses by a memory cell 19 of the memory for possible further recording of the channel address and coding results when interrogating one of the subsequent channels of the device. By the same signal, through the seventh element OR 27, the third flip-flop 31J is reset, which leads to switching

0 output of the generator 18 pulses from work to the second distributor 28 pulses to work on the first distributor 32 pulses. In addition, the sixth element is unlocked again.

5 And 35 and the operating mode of the First Memory 5 is changing again. The signal from the fourth output of the first distributor 32 pulses increases the content of the first counter 7, and then the circuit goes to work on polling the next channel of the analog input system.

The survey of each of the channels may occur on a shortened version,

5 which was previously described by i-shi according to the above-described extended variant, when data coding is performed.

It should be noted that addressing

0 of the first memory block 5 is synchronized and in phase with the channel addressing of the device. And the second memory block 19 is addressed incrementally, starting with a zero address, as data is received from the output of the analog-digital converter 2. Moreover, two cells of memory are used to record each encoding result. The address 0 is entered in the cell with an even number.

five

0

five

My channel through which information was encoded, and the result of encoding the data is recorded in the next odd-numbered cell. In this case, since the coding occurs only on those channels where the difference with the result of the previous coding exceeds the tolerance, then the second data memory block 19 may appear to be recorded much less than the polled channels in the loop. It may be that the coding was not carried out on any of the polled channels, i.e. there was an empty polling cycle, as described earlier. In this case, the second counter 10 maintains a zero output at the end of the polling cycle, which is fixed by the comparator 13.

131A1872614

It should be noted that the multichannel-mounted second counter 10, and the analog input device is inst-ing, because at the end of the formation octopus cycle, at the end of each cyclic channel, the second counter 10 is reset, the second trigger 17 triggers, therefore, reading begins is an exit-from zero address output. On the cut of the device information. The trigger pulse reading through the sixth element 17 is set to the unit co-OR 29 increases by one the content from the output of the first element 8 to the second counter 10, which is ready to be compared only if the address for reading data from the next exit the second counter 10 of the non-equating cell of the second block 19 is paneled, which is realized by the third element.

volume I 23, therefore, resetting the second account ™. Since the address of the first 10 is read into the zero state with the goal of receiving new preparation for the reading procedure, 15 information, and then the data word, it is also carried out from the output of the first the software exchange of the comparison element 8 through the first ele-e-easily formed using the register OR 22 and through the element 14 of the delayed operations the object cell address, the main memory, which, at the end of the polling cycle, the channels 20 are retrieved

device at the time of the memory of the memory block 19; data. New Comparison Element 8

a census of the final address of the second On reaching the second counter

of block 19 of the memory from the second counter of the address of the last cell in which the buffer register 24 “Storage 25RO” still had information after

the final address of the entered data read these data content

in block 19, the memory required for the counter. 10 is increased by one

performing the reading procedure at a time becomes equal to the content. So, at the end of the pro- fer register 24. The data coding procedure is triggered. The QOR ° comparison element 16 is received, and the fourth element OR 26 resets the device and the single output-second trigger through the zero readout output 17, which leads to the recording of information of the device, resetting the information readiness signal, which will be removed after reading. This is perceived by the system control data from the second memory block 19 ac signal to stop Proprio new cycle of channel scanning, taktsedury reading. An impulse from the output as there are no hardware obstacles of the second-side comparison element 16 through the next polling cycle of the OR element 22 and the delay element 14 of the cell, without reading the data from the block 19, the second memory is again reset. the case of the counter 10 "Now the device half-resetting the second trigger 17 is returned to its original state from the output of the second element and is ready for a new comparison polling cycle through the fourth channel element"

OR 26. The question of necessity. It should be noted that the new launch

reading the array should be resolved;

rammno, as result of the analysis is specified - to a synchronous entrance from the system timer,

system outputs of the device. so and to the addressed recording entry

Is entering a new word-state

Reading the data set is carried out - maintaining the same

via the system data bus with output-i

Yes, the second block of memory 19 is complete; 50 Thus, the compression procedure

the survey cycle of channels in modeledanny, carried out in anapogovoy

reading. Reading a word in an implemented form at the input of a multichannel one is done by sending a signal to the analog information collection destination,

the reading input, which allows the data to be compressed due to excludes, at the first input, the fifth element gg of excess samples in time,

OR 30. From the output of the fifth element, about half the input time 30, a sync signal is generated for information and to increase the BiPoporo production bandwidth of memory block 19. When this part of the high-frequency channel is released, the word is read at the address of the device.

7

the output of the first counter 7 goes to the address inputs of the switch 1 and the first memory block .5, then the addressed channel is switched from the first output of the first distributor 32 pulses to the signals from the first output of the distributor 32 pulses and the memory channel of the memory 5 to the digital-analog converter 4 data words, i.e. The first memory block 5 at this moment from the output of the third flip-flop 31 is held in read mode. During the specified operations, the analog signal of the addressed channel is fed to the analog-to-c (3) input of the dual converter 2 and to the first input of the 3-step signal analysis unit. . At the same time, the second input of the unit 3 for analyzing the increments of the signal from the output of the digital-to-analog converter 4 receives the analog equivalent of a data word read from the memory cell of the first memory block 5 with the same address as the closed channel of switch 1. A time interval sufficient for completion of transients for analog signals, the pulse from the second output of the first distribution of the body of 3Z pulses is performed by gating the memory element 40 of the unit 5 for analyzing the signal increments. At the output of the analog block 3 Isa ratio signal is fixed increments the analog input signal at a given time and its values in predschuschy sampling time. If the difference between the signals is within the set tolerance, then a zero value is fixed at the control input of the unit 3 for analyzing the signal increments, otherwise it is a single value.

The output of the unit 3 for analyzing the signal increments goes to the enable inputs of the switch 6 and the first element And 9 and determines further

work scheme, g

With a small interval of time, the second output of the first distributor 32 pulses the control pulse that goes to the second input of the first element I 9 and to the S input of the first trigger 12. Regardless of the state of the control output of the signal increment analysis unit 3 the first trigger 1 will be set to one

 , 5 0 5 About

0 5

five

0

five

This means that the potential at the output of the readiness of the device changes, which indicates that the measuring part of the device is in the operating state and that the operation mode of the first counter 7 changes to the counting mode 1-1m. The second memory block 19 is transferred to the recording mode at the input of the operation mode, the inputs of the first 34 and sixth 35 H elements receive the resolving 1Y potential, which prepares these elements for the upcoming device operation cycles, the resolving potential is fed to the first element 9 The first element AND 9 of the pulse from the third output of the first distributor 32 pulses passes depending on the output state of the unit 3 for the signal increment analysis. If a . the first input element And 9 zero potential, then the signal at its output does not pass and, therefore, does not affect the further operation of the device. In this case, the subsequent signal from the fourth output of the first distributor 32 pulses through the sixth element And 35, which is already prepared with potentials the outputs of the first 12 and third 10 flip-flops, the unit is entered on the counting input of the first counter 7 This leads to a change in the address on the address inputs of the switch 1 and the first memory block 5. Since, in the future, the first distributor of 32 pulses works, starting again from the first input, the described operation cycle of the device repeats again, but with a different channel address, which is one more than the previous one. If, during the device operation, when polling all channels, the input the first element And 9 remains blocked by the control output of the signal increment analysis unit 3, then after a set number of such short cycles, the output of the first counter 7 is set to an address equal to the address written to the second group pp bits register of 20 states. This fact is revealed by the first comparison element 8, the signal from the output of which through the first element OR 22 clears the first trigger 12 and resets a number of other elements that did not work in the described empty channel polling cycle, and therefore the reset signal

9 1

element 8 of the comparison, only confirms their previously established state. The trigger 12 again switches the first counter 7 to the parallel recording mode, changes the signal at the device readiness output, blocks the fifth 34 and sixth 35 AND elements, but does not stop the operation of the first distributor 32 pulses. The next start of the cycle of operation of the device can be carried out via the system clock input from the timer through the second element 21 and the third element OR 25, since the contents of the state register 22 is saved and the second element 21 and is unlocked from the output of the high register 20. the launch can be carried out by writing a new state-word to the state register 20. It should be emphasized that the address mode of the device is provided by recording the word-state in which you record as the address of the first channel in the loop with the addressed channel address, and as hell, rez channel, to which must dlits cycle, address unit recorded more. In this case, after polling one channel, the device stops and returns to its initial state. It should also be noted that the asynchronous operation of the system sync-input and generator, pulses, which determines the operation of the first distributor of 32 pulses, does not lead to a faulty situation, since The new address at the output of the first counter 7 occurs on the fourth also the distributor 32, and the installation of the first trigger 12 occurs on the third cycle. Therefore, untimely attempts to overturn the first trigger 12 on the third cycle of operation of the first distributor 32 impulse9B and to start a new cycle of polling channels before the arrival of the system clock and parallel recording in the initial address counter 7 is not successful, since the first trigger 12 is kept in the reset state from the output of the first comparison element 8 potentially until a different code pattern is found in the inputs of the first comparison element 8, i.e., before parallel recording into the first counter 7 As a consequence the address ceiling elements, the first element AND 9

2610

the signal at its output is blocked, leading to the start of the analog-to-digital converter 2 and to the installation

the third trigger 31, does not appear,

Consequently, despite the fact that after the completion of the operation cycle of the device, the pulse generator 18 and the first valve distributor 32

continue to work, a faulty situation does not occur, since the asynchronous arrival of the system clock is synchronized and the influence of the outputs of the first distributor 32

pulses to the operation of the elements of the device are blocked until the arrival of a new system sync pulse or their arrival is indifferent to elements, such as

the period of the signals on the synchronous inputs of the switch 1 and block 3 of the analysis of the signal increments.

To synchronize the system clock and the first distributor

pulses 32 the duration of the system clock must exceed the cycle of operation of the first distributor 32 pulses., The system clock is gated by the signal from the fourth

the output of the first distributor 32 pulses on the second element I 21 Therefore, the recording of the channel address is parallel; in the polling cycle, before the new cycle of operation of the first distributor 32 pulses occurs

If in the process of polling the channels of the device, a single potential appears at the output of the signal increment analysis unit 3, then it is the signal from the third output of the first pulse distributor through the unlocked first element AND 9 (or the cleaved signal when polling the first channel in the cycle) enters the start input of the analog - digital converter 2 and to the installation input of the third flip-flop 31, which goes into one state. The single state of the third trigger 31 blocks the fourth 33 and sixth 35 elements AND prepares

unlocking the fifth element 34 and changing the operation mode of the first memory block 5, which goes from the read mode to the write mode. Despite the operation of the pulse generator 18, the device goes into standby mode until the encoding end signal arrives from the analog-digital converter 2o This signal through

15

Claims (2)

1. Multichannel analog information input device containing first and second switches, analog digital converter, pulse generator, first and second triggers, first and second memory blocks, first and second elements AND, first (OR element, first and second counters, element delays, the status register, the information inputs of the switch are the information inputs of the device, the output of the first switch is connected to the information input of the analog-digital converter, the output of the first OR element is connected to the input the delay element, the outputs of the first group of the status register are connected to the installation inputs of the first counter, the information inputs of which are the inputs of the initial installation of the device, characterized in that, in order to expand the scope of application by eliminating redundancy of the input information , digital-to-analog converter, third AND element, second, third and fourth elements of RShI, buffer register, first and second elements of comparison, comparator and synchronization unit, output The first multiplexer is connected to the first information input of the signal increment analysis unit, the second information input of which is connected to the output of the digital-to-analog converter, the inputs of which are connected to the outputs of the first memory block, the information outputs of the analog-digital converter are connected to the information inputs of the first memory block and information the inputs of the first .group of the second switch, the outputs of the first counter are connected to the address inputs of the first memory block, the information inputs of the second group the second multiplexer, the address inputs of the first switch, the inputs of the first group of the first comparison element, the output of the signal increment analyzer unit is connected to the first signal input of the second switch and the first input of the first element AND whose output is connected to the start input of the analog-digital converter and the first input of the synchronization unit. ten 15 20 55 1872616 the output of the conversion end of the analog-to-digital converter is connected to the first input of the second element OR and the second input of the synchronization unit, the output of the second element is connected to the synchronous input of the first memory block, the first output of the synchronization unit is connected to the synchronous input of the first switch and the second input of the second OR element, the second output with the synchronous input of the signal increment analysis block, the third output - with the read input - writing the first memory block, the quarter output - with the second input of the first element I and the installation input of the first 1 t iggera, fifth output - with a counting input of the second flip-flop, the output of the sches- - a second control input of the second com gutatora seventh output - with the second clock terminal block five 0 five five 0 five 0 memory, the eighth output - with the first input of the second element AND, the output of which is connected to the first input of the third element OR, the output of which is connected to the synchronous input of the first counter, the counting input of which is connected to the ninth output of the synchronization unit, the output of the first trigger is connected to the control input the first counter, the third input of the synchronization unit, the third input of the first element I, the input of the read-write of the second memory block and is the device ready output, the output of the first NIII Here, the output of the delay element is connected to the reset input of the second counter, the outputs of which are connected to the address inputs of the second memory block, the inputs of the comparator, the information inputs of the buffer controller and the inputs of the first group of the second comparison element, the inputs of the second group of which are connected to the outputs of the buffer the register, the outputs of the second switch are connected to the information inputs of the second memory block, the outputs of which are the information outputs of the device, the reset inputs of the status register and the buffer register, the first and fourth inputs of first OR input and a fourth sync block are reset input device, an output of second comparison element is connected to the second input of the fourth and the first OR element, an output of first comparator coupled to the third WMOs the house of the first OR element, the synchronous buffer register and the first input of the third AND element, the output of which is connected to the installation input 1 of the second flip-flop, the output of which is the device information readiness output, the output of the fourth OR element, is connected to the reset input of the second trigger, the comparator output connected to the second input of the third element And, the outputs of the second group of the state register are connected to the inputs; the second group of the comparison element, the output of the state register is connected to the second input of the second element And. the trigger input of the pulse generator; whose output is connected to the fifth input of the synchronization unit, the third input of the second element AND is the synchronous input of the device, the synchronous input of the state register and the second input of the third; the OR element is the recording input; the device, the sixth input of the synchronization unit is the read input of the device, the synchronization block contains the third trigger, the first and second pulse distributors, the fourth, fifth and sixth elements Hj, the fifth, sixth and seventh elements OR, the installation input in 1 of the third trigger is the first input of the synchronization unit, the direct output of which is connected to the first inputs of the fourth, fifth and sixth elements And is the third output of the block, synchronization, the second inputs of the fourth and fifth elements of And are the fifth input of the synchronization unit The output of the fourth element I is connected to the input of the first pulse distributor, the first, the second and third outputs of which are the first, second and fourth outputs of the synchronization unit, respectively; the fourth output of the first pulse distributor is connected to orym input of the sixth AND gate and the output is the eighth sync block, the output of the sixth AND gate is the output of the ninth sync block, a third input of the fifth AND gate is the second five 0 50 0 five 0 five the input of the synchronization unit, the fourth input of the AND element and the third input of the sixth AND element is the third input of the synchronization unit, the output of the fifth AND element is connected to the input of the second pulse distributor, the first input of which is connected to the first input of the fifth OR element, the output of which is the seventh the output of the synchronization unit, the second output of the second pulse distributor is connected to the first input of the sixth OR element, the output of which is the fifth output of the synchronization unit, the third output of the second pulse distributor with one with the second input of the fifth OR element and is the sixth output of the synchronization unit, the quarter output of the second pulse distributor is connected to the second input of the sixth OR element and the first input of the seventh OR element, the second input of which is the fourth input of the synchronization unit, the output of the seventh OR element with the reset input of the third trigger, the third inputs of the fifth and sixth elements OR are the sixth input of the synchronization unit. 2. A device according to claim 1, characterized in that the signal increment analysis block comprises an operational amplifier, an emitter follower, a threshold element, a signal level matching node, a memory element, a direct input of the operational amplifier is the first information input of the block, an inverse input of the operational the amplifier is connected to the potential input of the threshold element and the output of the emitter repeater, whose input is connected to the output of the operational amplifier, the input of the threshold element is the second information input of the block Ok, the output of the threshold element is connected to the input of the node of the signal level matching, the output of which is connected to the information input of the memory element whose synchronous input is the synchronizing input of the block, the output of the memory element is the output of the block Fig: 2 ) --g- janucb with AO axis - states ± L Ustanook on the main channel arch channel switching, recording D / A data from a poll of yes. ± Interrogation of the signal increment analysis unit. installation of the trieer / Output State of anaaise increment Device channel increment Not  End of cycle y Installed on the system signal Readiness of the measuring system Analysis of the state of the a-res. mka, memory one Aa / Mspfi i3HUe memory address block jT dstanZa system sienal; Mass fitness of the bath) Yes one BySem Does New Survey, ScrAioV from Record noZoeo sAo8a one Run ADC I ™ Y Record pesijAbmama coding S 1-s and SAOK memory ommutation of multiplexer Jl Record up to the second block of the address address onpouiitScL e-moe channel L KoMMymau ufl mulgli / and eksora and modification of the address 2-80 local mi / ± Writing So 2nd Memory SAOK I Modidzikacil address 2nd e0 SAQKQ memory Not one ) (wounded by masses) j ---- Snooker j Ft C Start}  Reading slobo (addresses) iu dmoposo memory block Auto-increment modification of the address of the Second memory block of the SloZa (data) from the Smopo memory block. An incremental modification of the address of the Second 5th memory block No / Last address 8 nassiVB Yes information / Signal output, ToToNvity- data set, o1 n1 / lrnie address su.-eo block of frame Thebes. five With food}