SU1728866A1 - Input-output device with checking errors and correction - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in the equipment for transmitting, receiving and processing information. The aim of the invention is to extend the functionality by providing a retransmission of a packet of information from it for a dynamic display. For this purpose, a device containing the first counter, two registers, a checksum calculation unit, two AND elements, a multiplexer, a bitwise summation unit, a bitwise comparison unit, an error indication trigger, three buffer transmitters, two parallel comparison units, an output trigger from memory, checksum trigger, display resolution trigger, memory control trigger, check bit calculation block, two RAM blocks, two transcoding memory blocks, a group of N indicators, three decrypt Ora, second, third, fourth, fifth and sixth counters. 2 Il.

Description

The invention relates to computing and can be used in the equipment for transmitting, receiving and processing information.

The aim of the invention is to enhance the functionality by providing retransmission of a packet of information and its dynamic indication.

Figures 1 and 2 depict an electrical functional diagram of an input / output device with error control and indication.

The device contains the first counter 1, two registers 2 and 3, block 4 of the checksum calculation, two elements AND 5 and 6, multiplexer 7, block 8 of bit sum, block 9 of bit comparison, trigger 10 of the error sign, and the output

multiplexer 7 is the serial information output of the device, and the information input of the block 8 of sequential summation is the serial information input 11 of the device, three buffer transmitters 12-14, two blocks 15 and 16 of parallel comparison, the trigger 17 of the output from the memory, the trigger 18 of the control amounts, display resolution trigger 19, memory control trigger 20, control bit calculation block 21, two RAM blocks 22 and 23, two transcoding memory blocks 24 and 25, three decoders 26-28, second 29, third 30, even erty 31, fifth 32 and sixth counters 33, wherein the first count input of counter 1 is input to the recording apparatus of feature 34, an information input of the first

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the operational memory unit 22 is the first device data input 35, the output of the first counter 1 is connected to the information input of the first buffer transmitter 12 and the first information input of the first parallel comparison unit 15, the second information input of which is connected to the output of the first buffer transmitter 12, which, besides In addition, it is connected to the address input of the first memory block 22, the outputs of the second 13 and third 14 buffer transmitters, the address input of the second memory block 23 and the first information input The second side of the parallel comparison unit 16, the output of which is connected to the reset input of the display enable trigger 19, the installation of the checksum trigger 18, the reset output of the memory trigger 17, and the output of the first memory control trigger 20 is connected to the control the first 15 and second 16 parallel comparison units, the first permitting inputs of the first 12, second 13 and third 14 buffer transmitters, and the reverse access inputs of the first 22 and second 23 operating units 22 and 23 memory, reset input trigger 20 memory management is the input 36 of the input data, the installation input of the trigger 17 output from the memory input 37 command output device, the output of the trigger 17 output from the memory connected to the first input of the first element And 5 , the first input of the installation of the trigger 20 of the memory management and the first input of the reset of the trigger 10 of the error indication, the second input of which is connected to the input 34 of the device record, as well as the second input of the installation of the trigger 20 of the memory management, the second permitting inputs of 12 and the second 13 buffer transmitters and the recording resolution input of the first RAM block 22, the output of which is connected to the first information input of the first register 2, the first information input of the multiplexer 7 and the output of the second RAM memory 23, the information input of which is combined with the first information the input of the bitwise comparison unit 9 and the operation input of the bitwise summing unit 8 and forms the second device data input 11, the output of the bitwise summing unit 8 is connected to the second information onnym input of the bit-wise comparison, the output of which is connected to the trigger input 10 of feature installation errors, the output of which is the output

38 of the indication of a device error, the first output of the first register 2 is connected to the information inputs of the second register 3, unit 4 of the checksum calculation and

block 21 calculation of the control bits, the output of which is connected to the second information input of the first register 2, the second output of which is connected to the second information input of the multiplexer

07, the first control input of which is connected to the output of the first element 5, the output of the first decoder 26 is connected to the second input of the first element 5, the first input of the second element 6, the mode inputs of the first 2 and second 3 registers, the counting inputs of the second 29 and the fourth 31 counters, the reset input of the checksum trigger 18, the second control input of the multiplexer 7 and the control input of the block

0 4 checksum calculation, the input of the first decoder 26 is connected to the output of the third counter 30, the output of the checksum trigger 18 is connected to the second input of the second element AND 6, the output of which is under5 keys to the third control input of the multiplexer 7, the third information input of which is connected to the output block 21 for calculating the check bit; the output of the second counter 29 is connected to the information input of the second buffer transmitter 13; the first and second outputs of the second register 3 are connected to the address inputs of the first 24, respectively. and the second 25 recoding memory blocks, the output of the first

5 of the transcoding memory unit 24 is connected to the information inputs of the odd group indicators 39, the output of the second transcoding memory unit 25 is connected to the information inputs of the even indicators 40

0 group, the output of the fourth counter 31 is connected to the input of the second decoder 27, the output of which is connected to the control inputs of the group indicators 39 and 40, the enable input of the output trigger 17

5 from the memory and the installation input of the display resolution trigger 19, the output of which is connected to the access permission inputs of the first 24 and second 25 transcoding memory blocks, input 36 of the input feature

The device data 0 is connected to the reset input of the fifth counter 32 and the counting input of the sixth counter 33, the output of the fifth counter 32 is connected to the information input of the third buffer transmitter 14 and the second information input of the second parallel comparison unit 16, the output of the sixth counter 33 is connected to the input of the third the decoder 28, the output of which is connected to the counting input of the fifth counter 32, allowing the input of block 8 bit

summation, the write control input of the second RAM block 23 and the control input of the bit-compare unit 9, the clock inputs of all counters 1, 29-33, the registers 2 and 3, and the trigger inputs 10.17-20, as well as the clock inputs of the checksum calculation unit 4 and a bitwise sum block 8 are combined to form the local synchronization input 41 of the device.

Counter 1 is used to select the address of the RAM cell and store the number of bits recorded in the RAM. The counter 30 and the decoder 26 form a synchro sequence (pilot signal) designed to synchronize the display and output nodes. The counter 29 samples the address of the block 22 or 23 in the display or output mode. Counter 31 commutes indicators (power). Registers 2 and 3 are designed to output information from block 22 in display and output modes. Blocks 24 and 25 form a special binary code of input / output information from the binary code to feed to indicators 39 and 40. Multiplexer 7 commutes at the required time intervals (according to the pilot signal) useful and service information (check bit for each useful byte information and check byte) in output mode. Counter 33 and a decoder form a synchronization sequence designed to identify useful information and the check bit in a packet of serial information received via bus 11. Counter 32 samples the counter address of block 23 during reception of a packet from bus 1.1, and then stores the value the number of bits recorded in block 23. The trigger 20 is intended to switch the outputs of block 22 or 23 to an indication.

Conventionally, the device can be divided into an information recording unit (for example, from a keyboard) in block 22 of the transmitting part (counter 1, buffer transmitter 12, block 22 of memory), display unit (block 15 or 16, block 22 or 23, depending on the indication mode : dialed or received messages, registers 2 and 3, blocks 13, 19, 24, 25-27, 29-31, 39 and 40), information output node from block 22 to the serial bus (blocks 2, 3, 4 , 21, 29, 13,30,26,7, 17, 18, 5, 6 and 15), the node for entering information on the serial bus 11 (blocks 32, 33, 28, 14, 23.8 and 9). The information output unit from the RAM unit and the input unit from the serial bus constitute the shared-use line controller (LPC).

Consider the mode of recording information on the bus 35. The incoming serial code (word) is accompanied by a recording indication signal (bit-by-bit) on the memory bus. For the gates of the recording feature, the sequential code (from the keyboard) is fed to the information input of the block 22.

Consider the display mode information, which is also the storage mode recorded from the keyboard message. Counter 30 and decoder 26 form a pilot signal with a repetition period of 9T, a duty cycle of 8/9, and a discreteness of T, where T is the repetition period of the signal fed to the local synchronization bus VI. The pilot signal synchronizes the operation of the display units and the transmitting part of the LPC controller. The counter 19 through the buffer transmitter 13 generates an address code (from zero by R Kmax, where R is the word length of the message received from the keyboard. Kmax is the maximum number of words recorded from the keyboard in the 22 words block) via the address bus formed by the outputs of the buffer transmitters 12- 14, the inputs of blocks 15 and 16 and the address inputs of blocks 22 and 23. During the eight periods T in the subclot tc, the counter 29 increments its contents, during the ninth (last) discrete T in the subcycle tc, there is a timeout, the assignment of which in the output mode to the bus - formation and bitstaffing in serial output control bits information in the LPC. In sync with the counter 29, the counter 31 and the decoder 27 generates signals for sequential switching (switching) of pairs of indicators 39 and 40, the minimum number of sections of the indicators is 0.5 Kmax under the condition of outputting numbers in binary-hexadecimal or binary hexadecimal form on the LPC. The cycle of operation of the counter 31 is TC 9T (0.5KMax + ch), where t is the checksum volume at the end of the message. The information byte displayed in the current sub-cycle during the interval of 8T is written sequentially to register 2, where during the last (ninth) sampling of the current sub-cycle tc is stored and in parallel is fed to the input of the block 21 for calculating the logical value of the control (ninth) bit ( in the LKP output mode), to the parallel inputs of the register 3 for storing and storing during the next subcycle tc, to the counting inputs of the checksum calculation unit 4 (used in the LKP output mode). From register 3 in the next sub-cycle tc, the information goes through blocks 24 and 25 to the corresponding buses of indicators 39 and 40. In this mode, the current cell address code of block 22 from the address bus goes to the information inputs logaR Kmax-bit unit 15, to the second information inputs which the contents (number K) of counter 1 arrive. In the cycle of indication, a continuous comparison of the number K stored in counter 1 with the current code value on the address bus occurs. If these codes are equal, trigger 19 blocks further indication of tech 1C present cycle. The blocking of the indication is carried out by applying the off signal to the corresponding control inputs of blocks 24 and 25. The blocking of the indication is released in the next cycle 1c at the beginning of the second sub-cycle tc. The duration of the continuous illumination of each pair (section) of the indicators 33 and 40 is 9T with a scan ratio of Q (0.5 Kmax + t) 2

Consider the mode of displaying sequential information on L KP. On the bus 37 to the input of the installation of the trigger 17 enters asynchronously (relative to the phase of the cycle t.c) command Output, the duration of which should not be less than the duration of t.c. The trigger 17 can be set only at the beginning of the first sub-cycle tc of the cycle tu of indication, implementing the phasing of the process of displaying information on the LCP and on the indicators. From the first to the 0.5 K th subcycle, tc, every first eight clock periods, is output from block 22 and transmitted through serial information multiplexer 7. In each ninth clock period of each sub-cycle tc with numbers from the first to 0.5K multiplexer 7, it performs bitstaffing of the control bit from the output of block 21 and adds the current information byte to the previous result of the summation in block 4. When the counter contents are equal 1, the code on the address bus clears trigger 17, stops outputting information from block 22 to LPC, and sets trigger 18 to output the checksum accumulated in block 4 to LPC. During the ninth clock period of tc, the number will be labeled ohm 0.5K, information is output to the parallel inputs of register 2, from which, in a sequential form, the information during the first eight clock periods of the tc sub-cycle (the number (0.5K + t) is transmitted via multiplexer 7 on the LCP. the amount is carried out as described above. The output process on the LPC ends with resetting the flip-flop 18.

Consider the mode of entering information from the LPC. Upon receipt from the LPC of the reception sign (bus 36), the counter is initialized.

33 and a decoder 28 that form a sync sequence with the sync sequence parameters of the transmitting part. The reception must be set for the entire duration of the reception. During each of the first eight clock periods of the synchronization sequence, the counter is incremented by 32 the number of received information bits (minus the control bits).

In block 8, the input information is sequentially added for each of the first eight clock periods of the synchro sequence. In each ninth clock period of the synchro sequence, in block 9, the accumulated result of the summation is compared with the current value of the control bit on the LPC. the contents of block 8 are zeroed out. Upon completion of the input, the number of received information bits is stored in the counter 32, and the trigger 20 switches the block 16 to compare neither to the reset input of the trigger 19 and turns off the block 15, blocks the buffer transmitters 14 and 12, connects the output of block 23 to the serial input of register 2 and turns off the output of block 22.

On the address bus, the address code in the display mode, which is initialized automatically upon completion of the input process, goes to the address inputs of block 23, information from the output of which goes to indicate registers 2 and 3. The display node switches again to display the contents of block 22 after the first arrival information on bus 35 or when reinitializing the output process by setting trigger 20. In the reception process, due to the distortion of the input information, it is possible to install trigger 10, which is reset tech installation trigger 20.

Claims (1)

Invention Formula An I / O device with error control and indication containing the first counter, two registers, a checksum calculation unit, two AND elements, a multiplexer, a bitwise summing unit, a bitwise comparison unit, an error indication trigger, and the multiplexer output is a serial information output device, and the information input of the block summation block is a serial information input of the device, characterized in that, in order to extend the functionality by providing Liver of packet retransmission and its dynamic indication, it contains three buffer transmitters, two parallel comparison blocks, a memory output trigger, a checksum trigger, an indication resolution trigger, a memory control trigger, a check bit calculation block, two RAM blocks , two transcoding memory units, a group of N indicators, three decoders, second, third, fourth, fifth and sixth counters, so the counting input of the first counter is the input sign of the device record, info mation input of the first operational unit is a memory device a first input data, a first counter output. connected to the information input of the first buffer transmitter and the first information input of the first parallel comparison unit, the second information input of which is connected to the output of the first buffer transmitter, which is also connected to the address input of the first RAM block, the outputs of the second and third buffer the transmitters, the address input of the second memory block and the first information input of the second parallel comparison block, the output of which is connected to the reset input of the enable trigger indication, the input of the check sum trigger, the reset input of the memory outlay trigger, and the output of the first parallel comparison block, the output of the memory management trigger is connected to the control inputs of the first and second parallel comparison blocks, the first enabling inputs of the first, second and third buffer the transmitters and the access enable ports of the first and second RAM blocks; the reset input of the memory control trigger is the input of the data entry feature; the input of the trigger setup from the memory is the input of the device output command, the output of the memory outlay trigger is connected to the first input of the first element AND, the first input of the memory management trigger installation and the first reset input of the error indication trigger, the second reset input of which is connected to the input sign of the device record, as well as the second input of the memory management trigger, the second enable inputs of the first and second buffer transmitters, and the write enable input of the first RAM block whose output is connected to the first information input to the first register, the first information input of the multiplexer and the output of the second RAM block, whose information input is combined with the first information input of the block bitwise comparison and the input of the operation of the unit of bitwise summation and forms the second data input of the device, the output of the unit of bitwise summation connected to the second information input of the one-bit comparison unit, the output of which is connected to the installation input of the error symptom trigger, the output of which is the output of the device error indication, 0 the first output of the first register is connected to the information inputs of the second register, the checksum calculation block and the check bit calculation block, the output of which is connected to the second information input of the first register, the second output of which is connected to the second information input of the multiplexer, the first control input of which is connected to the output of the first element And the output of the first decoder is connected to the second input of the first element And the first input of the second element And the inputs of the mode of the first and second registers, Aerial inputs of the second and fourth counters, trigger reset input 5 of the checksum, the second control input of the multiplexer and the control input of the checksum calculation unit, the input of the first decoder is connected to the output of the third counter, the output of the trigger 0 checksum is connected to the second input. the house of the second element And, the output of which is connected to the third control input of the multiplexer, the third information input of which is connected to the output of the block 5 calculating the check bit, the output of the second counter is connected to the information input of the second buffer transmitter, the first and second outputs of the second register are connected to the address inputs of the first and second transcoding memory, respectively, the output of the first transcoding memory is connected to the information inputs of the odd group indicators, output of the second memory block 5 transcoding is connected to the information inputs of the even group indicators, the output of the fourth counter is connected to the input of the second decoder, the output of which is connected to the control inputs of the group boats, the enable input of the output trigger, and the input of the display enable trigger, the output of which is connected to the inputs permitting the first and second 5 transcoding memories, an input of the data entry feature of the device is connected to the reset input of the fifth counter and the counting input of the sixth counter, the output of the fifth counter is connected to the information input of the third buffer transmitter and ПТ ° лРЛГЛУ пФ ° РмматуУ BX ° W blo ° to the RAM memory unit and the control of the parallel compression. VMUPP tag- ™ g, l „,, to parallel comparison, the output of the sixth meter is connected to the input of the third deM IRJ4Cn K.f, m wivsixt wrinAUUDAU / lEal UIIUKd COMPUTED emGwhol1X; ЯТ ° GOSCHETCHIKA ACCORDING TO-5 KONTR ° LNNY of the sum and block of a bit the secondary input of a random summation-summation unit are combined to form the input nor, the control input of the device's second-hand synchronization. input comparison block, the synchronous inputs of all counters, registers and triggers, as well as the synchronous inputs of the calculating unit memory unit and control r, l „,, to f, m wivsixt wrinAUUDAU / lEal UIIUKd CALCULATED CONTRACT ° OF THE LUNG AMOUNT AND THE UNIT input comparison block, the synchronous inputs of all counters, registers and triggers, as well as the synchronous inputs of the calculating unit S in yd FIG. 2 35