SU1298869A2 - Programmable pulse generator - Google Patents

Abstract

The invention can be used as a source of radio signals with predetermined laws of the envelope and phase of a radio pulse in various areas of radio engineering and is in addition to as. No. 1248029. The purpose of the invention is to improve the accuracy of signal formation. The programming generator contains information input unit 1, operational storage units 2 and 12, digital-to-analog converters 3 and 13, address generation unit 4, analog storage unit 5, decoders 6 and 11, readout distributor 7. In addition, the device includes an AND 8 element, a clock pulse generator 9, a waiting multivibrator 10, an adder 14, a subtractor 15, an analog-to-digital converter 16, and a delay element 17. The introduction of a gating pulse generator 18, a low-pass filter 19, and an amplifier 20 makes it possible to automatically compensate for the dynamic nonlinearity of analog switches. 2 Il. (L

Description

The invention relates to a pulse technique, can be used as a source of radio signals with predetermined laws of variation of the envelope and phase of a radio pulse in various areas of radio engineering, in particular in the field of radio communication and radar, and is an improvement of the invention according to the author. St. No. 1248029.

The purpose of the invention is to improve the accuracy of signal generation using automatic compensation of dynamic nonlinearity of analog switches.

FIG. 1 shows a functional diagram of a programmable generator 15 (ADC) 16, a digital output and

pulse shaker; in fig. 2 - block diagram of the input information.

The programmable generator contains information input unit 1, an operational storage unit (OZB) 2, whose information input is connected to the information output of unit 1, a digital-to-analog converter

the sync output of which is connected respectively to the digital input input and the recording input of the OZB 12, the synchronization input of the A / D converter 16 is connected 20 via a delay element 17 to the first synchronization output of block 1, the control output of which is connected to the third input of the AND element 8 and the control input of the D / A converter 13, information

(DAC) 3, the information input of which to the output of block 1 is connected to the output of OZB 2, block 4 of the formation of an address, the information input of which is connected to the information output of block 1, the first sync output of block 1 is connected to the write input of OZB 2, the second sync output is connected to the gate input of block 4, the third synchronization output of block 1 is connected to

also the information input of the distribution of 7 read pulse, the third synchronization input of which is connected to the second output of synchronizer 30 of block 1,

The 18 gating pulse shaper is connected to the generator 9 clock pulses by an input, and the output to the fourth input by the synchronizing input of block 4, the address sampling of the distributor 7, the terminal of which is connected to the address equalizing input of the ramp 18 of the OZB 2 connectors , analog memory dinen with control output of block 1, block (AZB) 5, the address inputs of the regeneration of which are connected to the outputs of the decoder 6 of the regeneration address, the inputs of which are connected to the corresponding outputs of block 4, the output of the AZB 5 is the output of the device -keeping, 19 rasprefiltr lowpass output connected to the input of amplifier 20, whose output

0 go to the second input of the subtractor 15, and the input of the filter 19 is connected to the output of the AZB 5.

The information input unit 1 controls the operating modes of the device and can

the read pulse divider 7, whose address outputs are connected to the corresponding address inputs of the AZB 5, the AND 8 element, the first input of which is connected to the clock pulse generator 9, and the output to the information input perBlock 1 controls the operating modes of the device and can

45 consist (fig. 2) of a digital computer of a computer 21, allowing to write the code corresponding to the value of signal S (t) in OZB 2 or the required installation address

the first synchronization input of the distributor - 50 block 4, as well as the generation of the perioditor 7, the waiting multivibrator 10, the output of which is connected to the second input of the And 8 element and the second synchronization input of the distributor 7, the railway input, the slider of the multivibrator 0 is connected to the output of the I1 decoder, information inputs which is connected to the address outputs of the distributor 7.

The generator also contains the second OZB 12, the address inputs of which are connected to the address inputs of the OZB 2, and the outputs of the second OZB 12 are connected to the information inputs of the second DAC 13, the output of which is connected to the second input of the accumulator 14, the first input of which is connected to the output of the DAC 3, the output of the adder 14 is connected to the information input of the AZB 5, the subtractor 15, the first input of which is connected to the output of the DAC 3, the output of the subtractor 15 is connected to the analog input of the analog-digital synchronization converter which is connected respectively to the digital channel o- vomu Valid Valid entries EHS and 12, the clock input of the ADC 16 is coupled through delay element 17 to the first output synchronization unit 1, whose control output is connected to the third input of AND gate 8 and the control input of the DAC 13, the output of information Ziona unit 1 connected

also the information input of the readout distributor 7, the third synchronization input of which is connected to the second synchronization output 30 of block 1,

The gating pulse generator 18 is connected to the generator of 9 clock pulses by an input, and the output to the fourth synchronization input of the distributor 7, and the control input of the driver 18 is connected to the control output of the unit 1,

the low-pass filter 19 is connected by an output to the input of the amplifier 20, the output of which is fed to the second input of the subtractor 15, and the input of the filter 19 is connected to the output of the AZB 5.

The information input unit 1 controls the operating modes of the device and can

45 consist (fig. 2) of a digital computer of a computer 21, allowing to write the code corresponding to the value of signal S (t) in OZB 2 or the required installation address

A sequence of pulses from the third synchronization output, the decoder 22 connected by information inputs to the control bus 55 of the computer 21, the outputs of the decoder 22 are the synchronization outputs of block 1, the OR element 23 connected to the outputs of the decoder 22, and its output is connected to the sync input terminal

on the periphery (Clffi) of the computer 21, through the delay element 24, the output of the computer 21 is connected to the gate input of the decoder 22, the first output of which through the delay element 25 is connected to one of the inputs of the OR element 23, the information output of the computer 21 is the information output of unit 1, the first d bus UPR computer 21 is the control output of block 1,

Block 4 may consist of two binary 4-bit counters with state preset. The block AZB can be implemented in the form of parallel-connected n memory sampling devices with current keys at the output.

The read pulse distributor 7 may consist of a read address address generator and an address decoder connected in series.

The generator works as follows.

There are two modes of operation: write-adjust and read-regeneration. Mode is set by block

In the recording-correction mode, the computer 21 controls the generator-correction-correction mode, sets the required address code and enters the required information at this address in the SSS 2, and then starts the operation of the A / D converter 16 to convert the error into a digital code and record it in the SAT 12. At the information output of block 1 exposes the address code of the cell OZB 2, while programmatically on the UPR line of the computer 21 exposes information 00000001 (binary), then the computer 21 emits a pulse BB, which is decoded, passes to the second synchronization output of block 1 and record1) Shat information in block 4 and distributor 7.

After that, the computer 21 on line X exposes the necessary information in binary code for recording in OZB 2, corresponding to the instantaneous value of the signal S (t), while the information 00000000 is programmed on the UPR line and the pulse BB of the computer 21 passes to the first output synchronization unit 1 and writes the code in the appropriate cell OZB 2. At the output of the control unit 1 level logical zero, which prohibits the passage of pulses from the generator 9 through the element And 8 to the first input

ten

15

20

es

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synchronization (counting input) distributor 7.

At the same time, when writing the cell address code to block 4, the address code is written to the distributor 7, thus the corresponding cell of the AZB 5 is selected at the output of AZB 5. A logical zero at the control output of block 1 opens the output of the imaging unit 18, from which output pulses with a duty cycle equal to the number of cells, gates the distributor 7, as a result of which the analog key of the corresponding memory cell in AZB 5 operates in a real dynamic mode and output from AZB 5 I4; there is a sequence of unipolar pulses of amplitude E, which is With filter 19 and amplifier 20, it is highlighted for comparison with the reference level with D / A converter 3, since the address on AZB 2 of decoder 6 is the same. A logical zero at the control input of the D / A converter 13 causes the 25th output of the D / A converter 13 to go to zero level, i.e. The adder 14 is operated per pass, connecting the output of the DAC 3 to the analog input of an AZB 5. When an analog signal level is detected at the input of the subtractor 15, the difference between the reference level from CAC 3 and the level converted from some dynamic nonlinearity to AZB 5 is detected. This error must be converted to a digital code. For this, the pulse from the first sync output of block 1, which recorded information in OZB 2, delayed by time T in delay element 17, is longer than the set time:: fez in blocks 4, 6 and 7, conversion time to DAC 3, to AZB 5 and the filter 19, and the subtractor 15 starts the operation of the A / D converter 16, which, at time Tj, sets an error code at the information output, and at the synchronization output a pulse for recording information in the CIR 12, after which the error code of the corresponding (first) AZB cell is written 5 in the OZB 12.

The pulse from the first output of block 1 is delayed by time. the delay element 24 in block 1 and 55 arrives at the input of the CIP of the computer 21 after the time when the error code was recorded in the OZB 12, and the computer 21 can set the code of the next cell address (second) and record information about

thirty

40

45

50

the signal level in AZB 2 and the error level in AZB 12. This process is repeated until the entire volume of AZB 2 and OZB 12 is filled.

To set the read mode — regeneration of the computer 21 at the information output of unit 1, i.e. on line X, exposes O and on the UPR line information 00000011, the impulse BB is decrypted and passes to the third synchronization output of block 1. Since the CIP through the delay time arrives at computer 21, then the third synchronization output contains a periodic sequence of pulses with a period equal to delay time plus pulse duration explosives. This sequence changes the state at the address output of block 4.

The periodic sequence of pulses periodically changes the address in block 4, which allows you to sequentially poll the entire volume of OZB 2 and OZB 12 with the subsequent conversion of codes into instantaneous values of the signal using a DAC 3 and SchSch 13. The pulse period from the third output of block 1 multiplied the number of cells OZB 2, determines the time

regeneration, at the output of the D / A converter 3 and D / A converter 1330 from the zero address to the maximum in the regeneration mode are present. the maximum. The change of the address is the distribution signals, the period of which is equal to periolite 7 and, respectively, to the regeneration cell. Consider a more sub-AZB 5 occurs after the arrival of a clockwise regeneration process of its pulse from the generator 9 through

Suppose that the output of block 4 has 35 element AND 8. Upon reaching the distribution code of the address of the zero cell OZB 2, then the output of the DAC 3 is the instantaneous value of the signal, and this instantaneous value and address are saved until the next pulse arrives element B so that the clock name of the sync output output of block I., the generator 9 is not received from the generator 9, since the address inputs to the first synchronization input of the distribution of OZB 12 are connected to the address inputs of the divider 7 and the output of the AZB 5 goes - OZB 2, then the output of the DAC 13 is the level of the last cell, otorrhea long-, Wen dosing errors corresponding to (zero) of 45 female be zero, because during

A maximum voltage address is generated by the transmitter 7 at the output of the decoder 11, which triggers the multivibrator 10, which locks

ADB cells 5. And since the control input of the DAC 13 is logical 1 (on the UT1P bus 00000011), these two analog signals are summed in the adder 14 and fed to the analog input of the AZB 5. Due to the level error being analyzed when writing to the ADC 16 is signed, the addition of levels eliminates the dynamic nonlinearity of the analog key of the corresponding (zero) cell of the AZB 5. The decoder 6 connects the analog input of the zero cell of the AZB 5 to the output of the adder 14 i.e. recording takes place

the instantaneous value of the corrected signal in AZB 5.

The next recording cycle through regeneration time is regenerating.

After the next pulse arrives from the third synchronization output of block 1, the output of block 4 appears in the address of the first cell of AZB 2 and AZB 12, and with the help of a decoder 6

recording-regeneration of the instantaneous value of the corrected signal in the first cell of the AZB 5. This process repeats periodically with a regeneration period. Thus, in the CBA 5

all instantaneous values of the corrected signal are stored.

In order to restore this signal with the required period, serves

a readout system with AZB 5, consisting of a distributor 7, an element 8, an oscillator 9, a multivibrator 10 and a decoder 11. This system works as follows. Process

Reading information recorded in AZB 5 is performed by sequentially connecting the corresponding memory cells to the output of AZB 5 using the distributor 7 and pulses of the elec- tric element 8. At reaching the distribution, the element I is so that the clock pulses from the generator 9 do not arrive at the first the synchronization input of the distributor 7 and from the output of the AZB 5 is the level of the last cell, which must be zero, since during

A maximum voltage address is generated by the transmitter 7 at the output of the decoder 11, which triggers the multivibrator 10, which locks

pause no signal.

By varying the pulse duration of the multivibrator 10, it is possible to easily determine the duty cycle of the pulses. The end of the pulse. Opens the element And 8, and this front resets the distributor 7 to the starting address. In the process of reading-regeneration at the exit

55 control unit 1 is a logical unit level, which prohibits additional gating of the distributor 7 through its fourth synchronization input, since the output of the forwarder 18 is a constant level that opens the output of the distributor 7 to -skada.

Claims (1)

Invention Formula Programmable pulse generator auth. St. No. 1248029, about t. L and - due to the fact that, in order to increase the accuracy, the gating pulse former is entered into it UIR 22 Compiled by V. Chizhov Editor V, Petrash Tehred A. Kravchuk Proofreader L. Pilipenko Order 2246 Circulation 901 Subscription V1SHIPI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 and a series-connected low-pass filter and an amplifier, which are connected between the output of the analog storage unit and the second subtractor input, and the gate generator input is connected to the clock generator output, the output of the gate generator is connected to the third input pulse generator of the read signals ani. You are synr.1 You} (.. skl1lr, 2 was.. Y6 W. Managed Phage. 2