SU1451615A1 - Active power digitizer - Google Patents

Abstract

This invention relates to electrical measuring technology. The purpose of the invention is to increase the accuracy of conversion of active power to a digital code. The converter introduces a correction of the systematic additive error of the analog nodes of the converter, as well as a correction of the error of deviation from the calculated value of the conversion coefficient of the digital-to-analog converter 18. The introduction of the correction leads to the operation of the analog-digital converter 5 in almost one point. This allows a significant increase in the accuracy of the conversion result. A differential operational amplifier 4, a register 14, a third memory block 17, selectors 19, 20, and 21 are entered into the digital code of the active power converter. In addition, the converter contains a calibrated resistor 1, an analog switch 2, a source 3 of the reference voltage, an adder 6, amplifier 7, registers 8-13, memory blocks 15 and 1-6, shaper 22 pulses, reference frequency generator 23, counters 24 and 25 pulses, delay element 26 and control signal shaper 27. 2 Il. c (o

Description

de, yytsp, tsdp oy

the bias voltage of zero analog switch 2, analog-digital converter 5, digital-analog converter 18, differential operational amplifier 4, respectively,

DAC

   ADC

the calculated value of the conversion factor of the digital-analog converter 18;

systematic deviations of the real values of the conversion factors, respectively, of the digital-analogue

and analog-to-digital converters 18 and 5 from the calculated.

After multiplying D by 2 / N.,. the code of the correction value k k simultaneously with the entry in the register 14 is entered into the register 10 (FIG. 2p) where it is stored until the next interval for its determination.

The correction factor kv dits for error correction (t deviations from the calculated value of the conversion coefficient of the digital-to-analog converter 18. Periodically, after period T, the period T is determined, the definition of k. (Fig. 2c), during which the first input is added Differential Operational Amplifier 4 Analog Switch 2 Connected 5116158

- there is a voltage U from the output of the source 3 of the reference voltage, and in the register 9 the code of the number 5 ° A is recorded. At the end of the 1st cycle of the first step of sampling the period T, the code I is written to the register 13 from the outputs of the register 12 ( Fig. 2t), permitting the output to the outputs of 10 turns of the memory block 16 of the U code. k

 about AC P

pre-recorded at address 1. from the outputs of memory block 16, the code Uo kdts "is written to register 9 (Fig. 2i), after which the register 15 is reset to the zero state (Fig, 2p). The operation of the converter for T | performed similarly to that of T. As a result, by the end of the conversion 20 in register II a value code will be formed:

N

N

Korp Vop N, / 2, o-k,

 7 fj - °) (k ,, “, .A ,,, J (k ,,,., K ,, J- u, .k ,,. U, k Uok, 4, (I-uk, / k ).

After multiplying N by 2 / NT ° D, N Kop is simultaneously recorded in register 14 and entered in register 13, after which it determines the readout address of memory block 16, where the value of the correction factor is pre-recorded at this address

 1-lkts, "/ kts ,,, (4) Introduction in the proposed device of corrective velolotin and k and I". "

Kyor

thirty

35

40

in the process of converting signals on the current (by combining cresting with an alternate feedback analog converter), the conversion of the reference voltage addition leads to the operation of the ADC practical surroundings of one point C, which significantly clarifies the conversion

N

from

but. Dk - (N ,, -byts, p) (H “. + Uk ,,,) d + d -

A 1, 1 t ... TJ J

(kdl, + & kA ,,) + N.,,

 kАцn йk, 4 „/ cц,„ +) a „- a.Jk.A m-i dts„ i cd „ykl J„ / ccppp

“Op. (A“ -a „.,).

ADC

tsdp p U,

)

(k ,, / k ,;

one

where the deviation of the conversion coefficient of the converter I9 in the t-th sampling point of the input signal, taking into account both the multiplicative error and

tch k, cn (yk4, n / kts, n) x

(five)

50 tolerance

neonality.

At the same time, for periodic signaling of signals U (t) and i (t) about 55, the error will be transformed:

CPA

(3)

thirty

35

40

in the process of converting input signals at the current (m-th) sampling step, together with the introduction of negative feedback with a digital-to-analog converter of the previous result of conversion and addition of the reference voltage, which leads to the operation of the ADC almost in the vicinity of one point C, + ( a-a) allows you to significantly clarify the% e-conversion a

k

“Op. (A“ -a „.,).

ADC

A

tch k, cn (yk4, n / kts, n) x

(five)

50 error from nonlinearity.

In this case, for periodic inputs of signals U (t) and i (t) relative to 55, the conversion error will be:

(6)

4 CPA-jur

eh

 TS LPtssr

the mean values of the deviation of the conversion factor of the digital-to-analog 5 converter 18 from its calculated value during the conversion, respectively, i (t) and u (t)

formula of invention

ten

Active power to digital converter containing a calibrated resistor, analog switch, reference voltage source, analog-digital converter, summator multiplier, first-sixth registers, first and second memory blocks, pulse shaper, reference frequency generator, first and the second pulse counters, the delay element and the driver of the control signals, the first input of the analog switch being connected via a calibrated resistor to the input current line and the input of the pulse driver, and W The input is connected to the output of the reference voltage source, the output of the reference frequency generator is connected to the synchronization input of the pulse driver, the first input of the control signal generator and the input of the first pulse counter, the terminals of which are connected to the inputs of the first register and the second inputs of the control generator signals, and the setup input to the initial state — to the input of the second pulse counter and through the delay element — to the input of the recording control of the first register and the output of the pulse generator, the third inputs Drivers of the control signal generator are connected to the outputs of the bits of the second pulse counter, and the outputs respectively to the first to the third control inputs of the analog switch, the clock input of the analog-to-digital converter, the recording control inputs of the second to the sixth registers and the multiplier, to the resolution inputs of the third register, the adder, the first and second memory blocks, the inputs of the initial installation of the fourth, sixth registers, the inputs for selecting the first and second channels of the adder, the inputs

- five

-20

g - oo and

45161510

The third channel of which is connected to the outputs of the fourth register, the inputs of the fourth channel to the inputs of the fifth register, and the outputs to the inputs of the first channel of the multiplier and the inputs of the third and fourth registers; the inputs of the second channel of the multiplier are connected to the outputs of the first and second 10 memory blocks , and the outputs of the first and sixth registers are connected to the address inputs of the first and second memory blocks, respectively, characterized in that, in order to increase the accuracy of the conversion, a differential operational amplifier, digital the analog converter, the third memory block, the first to the third selector and the seventh register, with the third and fourth inputs of the analog switch connected to the input voltage board and common bus respectively, the first and second inputs of the complex 25 and the subtraction input of the differential operational amplifier are connected to the outputs of the analog switch, the source of the reference voltage and the digital-analog converter are 30 bodies, respectively, and the output is with the input of an analog-digital converter, the outputs of which are connected to the inputs of the first about the channel of the adder, the inputs of the second channel of which are connected to the outputs of the third register, the inputs of the third channel to the outputs of the first channel of the first and second channels of the second selector, the inputs of the fourth channel to the outputs of the third memory block and the outputs of the first channel of the third selector, and outputs with the inputs of the sixth register and the outputs of the third channel of the first selector, the outputs of the second channel of which ds are connected to the outputs of the first channel of the second selector and the inputs of the digital-to-analog converter, and the inputs to the outputs of the fifth reg country, the inputs of the second multiplier channel are connected to the inputs of the second register, the outputs of which are connected to the inputs of the second selector, and the outputs of the second channel of the third selector, the outputs of the third channel of which are connected to the inputs of the seventh register, and inputs to the outputs of the multiplier, in addition, the fourth control input analog switch, control inputs of the first - third selectors.

35

40

50

55

 b

6

- {l..J JlJTjn ... Ji

-1 7 |, 7-l

d

e

ё. Well

zJ

1 pg - lJ ITLJ --- glJ-LГlJ-LTLTLTTs- -Ll- and I I I I I I L.i LLLLJLLU LLLLLL II I

z

7

zJ

z

zf z

Claims (1)

Active power to digital code converter containing a calibrated resistor, analog switch, reference voltage source, analog-to-digital converter, adder multiplier, first to sixth registers, first and second memory blocks, pulse shaper, reference frequency generator, first and second pulse counters, a delay element and a driver of control signals, the first input of the analog switch connected via a calibrated resistor to the input current bus and the input of the pulse shaper, and the second input d to the output of the reference voltage source, the output of the reference frequency generator is connected to the synchronization input of the pulse shaper, the first input of the driver of the control signals and the input of the first pulse counter, the discharge outputs of which are connected to the inputs of the first register and second inputs of the driver of the control signals, and the input setting to the initial state - to the input of the second pulse counter and through the delay element - to the input control of the first register and the output of the pulse shaper, the third inputs form For control signals, they are connected to the outputs of the bits of the second pulse counter, and the outputs, respectively, to the first third control inputs of the analog switch, the clock input of the analog-to-digital converter, the write control inputs of the second sixth registers and the multiplier, the read enable inputs of the third register, adder, first and second memory blocks, inputs of the initial installation of the fourth, neck of the registers, inputs of the selection of the first and second channels of the adder, the inputs of the third channel of which are connected to fourth register moves, the fourth channel input - to the inputs of the fifth register, and outputs - to the input ⁵ of the first channel multiplier and the inputs of the third, fourth registers, the inputs of the second channel multiplier connected to outputs of the first and second fO memory blocks and outputs of the first and sixth registers are connected with address inputs of the first and second memory blocks, respectively, which, in order to increase the accuracy of the conversion, a differential operational amplifier, a digital-to-analog converter, a third block of pa memory, the first is the third selector 2Q and the seventh register, and the third and fourth inputs of the analog switch are connected to the voltage input bus and the Common bus, respectively, the first and second inputs of addition and the subtraction input of the differential operational amplifier are connected to the outputs of the analog switch, source reference voltage and digital-to-analog converter 30, respectively, and the output is from the input of an analog-to-digital converter, the outputs of which are connected to the inputs of the first channel of the adder, the inputs of the second channel to They are connected to the outputs of the third register, the inputs of the third channel - with the outputs of the first channel of the first and second channels of the second selector, the inputs of the fourth channel - with the outputs of the third 40 memory blocks and the outputs of the first channel of the third selector, and the outputs with the inputs of the sixth register and the outputs of the third channel the first selector, the outputs of the second channel of which 45 are connected to the outputs of the first channel of the second selector and the inputs of the digital-to-analog converter, and the inputs to the outputs of the fifth register, the inputs of the second channel of the multiplier connect 50 hours to the inputs of the second register, the outputs of which are connected to the inputs of the second selector, and the outputs of the second channel of the third selector, the outputs of the third channel of which are connected 55 to the inputs of the seventh register, and the inputs to the outputs of the multiplier, in addition, the fourth control input of the analog switch, control inputs first to third selectors, a seventh register write control input, initial input settings of the second, third and fifth registers, read permission inputs of the fourth register and 1 1 of the third read-only memory are connected to the corresponding outputs of the driver of control signals.