SU1398093A1 - A-d converter - Google Patents

Abstract

The invention relates to electrical measuring equipment and can be J / x, 0 ,,, L used to build accurate high-speed analog-to-digital converters, a device containing ATsrp 1, register 2.pam ,. ADP3, output register 4, delay element 5, amplifier 6, difference 5 ADC ;, 7, DAC 8, ROM 9, control unit 10 with, a digital adder 11, RAM 12, switch 13, .OR 14 and 14 are entered to increase accuracy and speed. exemplary signal generating unit 15. Improving accuracy is achieved by correcting additional conversion error with the introduction of an amendment in digital form, the sampling period is shortened due to the elimination of a number of nodes, and hence the delays introduced by them. in the process of conversion. The functionality is expanded by the introduction of nodes that provide a device self-correction mode, 2 h, n, f-ly, 2 pcs., 2 tabl. about from 00

Description

Ext. zaptssk.

Fig.}

The invention relates to electrical measuring technology and can be used to build high-speed analog-to-digital converters (ALP) of increased accuracy.

The purpose of the invention is to increase the accuracy and increase the speed 1.

FIG. 1 shows the functional NSC scheme of the analog-to-digital conversion device; in fig .. 2. functional scheme of the arithmetic logic unit (ALU),

An analog-to-digital conversion device contains ADC cf. 1 n high order bits, register 2 memory, ALUZ ;,. output N-р sp dnsh register 4, element 5 delay usshshtel 6 differences, ADC, 7 young bits, digital-analog converter 8 (1.No.), permanent memory 9 (ROM) j control unit 10, digital adder 11, operative spilling, its device 12 (RAM) j switch 13, element OR 14, block 15 for shaping the sample: signals executed on node 16 task p (,, block 1 m source 1B of reference voltage

12.

the contents of the RAM cells are zeroed

Consider the operation of the device in the mode of direct conversion of the input signal with a specific example. Assume that the number of bits of the entire device, including the sign bit, is the number of bits of the ADC. one

4, 7 N - n + m 8 (m 1, where m is the number of correction bits, see the known device), and the range U (-1.024 V) is (+ 1.024 V). Just as in the known device,

15, a coarse, high-speed integrated DAC is used here as node 8 (for example, 1118 PA1). The instrumental error of such a DAC is significant and is several times higher than the requirements imposed on node 8 as part of an analog-to-digital conversion device,

Let us assume that the values of the DAC 8 bit levels, taking into account their instrumental errors, are: U, 128-3125 mV; a 256 + 2 258 mV; t ns 512 - 4 508 mV; and „-1024 +

same knot “the first

16 task modes

hey: fi

19. second 20,

and

switch x „

Block 17 is made on the element

22g counter 23 ims lsov, element

And 24,

15 and generator 26

rj trigger

TH1.11TULSOV.

The control unit 10. consists of three series-connected delay elements, outlets; -;: the input of the first one through the generators is E-shuh .p: o ;; (connected to the outputs of the control device 10,

ALU 3 is performed on the element OR 27, the element And 28 and the digital adder-subtractor 29.,

The device operates in the 1: 1 section mode of nonlinearity of the quantization characteristic and in the direct conversion of the input signal U ,. In the first mode, all devices are involved in a vtorom — everything except the block 15 for generating exemplary signals, and the switch 13 is set to the E position, at which C is fed to the input of A1DP 1 s: h: gkly Record and Int. starting from the generator 2.6 pulses is not formed, but using the signal Obnulechch

+ 4 -1020 mV, the values of all the other levels of the DAL 8 are determined by the linear-3D combination of the discharge levels (the zero offset of the amplifier 6 of the third difference is assumed to be zero).

At the stage of fabrication and adjustment of the device CLI, as well as the known device, the instrumental errors of DAL 8, inherent in each output level, are determined experimentally under normal conditions and are recorded in digital form taking into account the 3Ha ka cell volume. 9. By address

each cell of the ROM 9 is the corresponding ADC code jp 1 (Table 1)

50

 55

supplied for a positive input signal U).

Let y be 640 mV. After strobe ADP 1, a code of +101 is formed, which is converted by the DAC 8 into a compensating voltage equal to 125 + 508 633 mV. The difference signal Uj, 640 - 633 7 mV, established at the output of the difference amplifier 6, after gating 7, is converted into the code +0000111 (+7 mV). By code +101, from cell ROM 9, with this address, the main error code is sampled (see Table O, equal to -111 (-7 mV), which is added to Cygnus 12.

the contents of the RAM cells are zeroed

Consider the operation of the device in the mode of direct conversion of the input signal on a specific example. Assume that the number of bits of the entire device, including the sign bit, is the number of bits of the ADC. one

n 4, 7 N - n + m 8 (m 1, where m is the number of correction bits, see known device), and the range U (-1.024 V) is (+ 1,024 V). Just as in the known device,

here, a coarse, high-speed integrated DAC is used as node 8 (for example, 1118 PA1). The instrumental error of such a DAC is significant and is several times higher than the requirements for node 8 as part of an analog-to-digital conversion device,

Let us assume that the values of the bit levels of the D / A converter 8, taking into account their instrumental errors, are: U, 128–3 125 mV; a 256 + 2 258 mV; t ns 512 - 4 508 mV; and „-1024 +

kch

supplied for a positive input signal U).

Let y be 640 mV. After strobe ADP 1, a code of +101 is formed, which is converted by the DAC 8 into a compensating voltage equal to 125 + 508 633 mV. The difference signal Uj, 640 - 633 7 mV, established at the output of the difference amplifier 6, after gating 7, is converted into the code +0000111 (+7 mV). Code +101 from ROM 9 is sampled with this address, the basic error code is sampled (see Table O, equal to - 111 (-7 mV), which is added in digital adder 11 with code A1Shd, p 7: 111 + 0000111 -fOOOOOO In this case, the output code of the entire device corresponds to an input signal of 640 mV, i.e. +101000000.

However, when operating a device (and a known device) in real conditions (other than normal), an additional component of the instrumental error of the DAC 8 and the amplifier 6 of the difference appears. Therefore, correction using ROM 9 loses effectiveness, Toe. incomplete compensation of the error and, as a result, the total error of the analog-digital conversion increases significantly (several times).

To correct the additional component of the instrumental error, the RAM 12 is inserted into the device, in the cells of which, in the nonlinearity correction mode, the quantization characteristics are entered into the error codes. Under the conditions of the above example, it can be assumed that the DAC levels U;

Lj, and U, in the presence of additional error, have changed and become equal: (J 125 - 2 123 mB; U 258 - 4 254 mV; L / 508 - 8 - - 500 mV; -1020 + 16 -1004 mV (change of the initial value is shifted the zero of the amplifier 6 difference is set equal to zero.) In the cells of RAM 12, additional error codes must be stored in accordance with Table 2.

When converting the input signal U to 640 mV, the following codes are obtained: 1: +101; ADC.

(corresponding difference 7: +0010001

the nominal signal -) (- (uL - (123 + 500) 17 mV); ROM code 9: -111 (see Table 1) and RAM code 12: -1010 (Table 2), after adding the codes 7, ROM 9 and The RAM 12 in the digital adder 11 will receive the code of the lower bits + 0010001-111-1010 +0000000, and the full code of the analog-to-digital conversion is equal to +1010000000, which corresponds to LJ | 640 mV,

The additional error codes are determined and recorded in the RAM cells 12 in the nonlinearity correction mode of the quantization characteristic. The device is entered into this mode by setting switch 13.

0934

position K. After that, from the output of the block 15, the formation of exemplary signals to the input 1 of the entrance 10

VT step voltage (values of exemplary voltage levels are chosen equal to the values of ideal DAC8 levels, and their number depends on the type of corrected error and is specified by the design of the block 17j, for example, to correct

the device zero bias error requires only one sample voltage of zero for

differential nonlinear correction. more - more levels).

The setting of the next exemplary voltage level is accompanied by a one-time start of the analog-digital conversion device (signal

Int. start), the formation of the code at the output of the digital adder 11, numerically equal to the value of the additional error, and recording it (recording signal) c. cell RAM 12, the address of which corresponds to the code MShsr 1 in this tact correction. When a signal arrives End trans. account- output of control unit 10

the establishment of the next level of reference voltage is permitted. After the formation of the last model voltage, the operation of the block 15 stops.

Example, believe that the input

device, not the input, but the i – e value of the reference voltage ({640 mV). Under the conditions of the influence of the additional error at the output

digital adder 11, we get the code, the equal sum of the ADC / ip 7 codes, ROM 9 and RAM 12 (the RAM code 12 is zero, since it has been explicitly reset), i.e. + 0010001-111 + 0 +0001010. This

the code corresponds to the opposite sign of the additional error of 10 mV (Table 2); the inversion of the sign of the code of the +1010 error can be made, for example, when performing the operation of addition in the working mode or

directly when writing code in

RAM 12. Then the received error code (+1011) is written into the cell of RAM 12 with the address +101, which corresponds to the ADC code cf 1.

The pattern signal generating unit 15 operates in the following manner.

The switches 19-21 in the node 16 task settings are set to

working position ;. When switching to the correction mode: m, switch 20 is repeated, cysts is in the opposite position, thus the process of zeroing RAM 12 is stopped and through the element 24 And 24, the trigger 25 is set to one:. In this case, the inhibit signal is duplicated on the first control generator generator 26 of pulses. Then, simultaneously with switch 13, the switch is switched to 1tel 19, thereby ensuring that the binary counter 23 is zeroed and a signal is given. This ensures a given accuracy under any environmental conditions, since it is possible to adjust to their changes. This advantage is manifested the larger the number of analog-to-digital conversion bits.

The formula of the gain

the control input is connected to the first output of the control loca- tion, the second output of which is connected to the 20th control input of the memory register, the outputs of which are connected to the corresponding inputs of the first group of inputs of the arithmetic logic unit, and the information inputs of the unified1. An analog-to-digital conversion device containing an analog-to-digital converter n senior

(logical O) at the first input of 15 bits, the information input of which element OR 22 and the second control element is combined with the input of the generator input 26 in block 17. At the output of block 15, the first value of the reference voltage U is set, After such preparation, the exemplary signal generating unit 15 is ready for the run.

When the switch 21 is pressed, the trigger 25 starts the generator 26, which provides periodic protection 25 with the corresponding inputs of the analog-digital converter's analog converter, fixed memory, and is connected to the corresponding outputs of the analog-digital converter 30 and older. Dov, the output of the delay element is connected to the first input of the difference amplifier, the output of which is connected to the information input ana; logo-digital converter young

model level U, forming 35 ™ Discharges, which controls the input of a source of 18 reference voltages

SRI, the overflow signal of the count 23 through the element And 24 translates the trigger 25 into a single state, stopped 40

call. In each step of the signal correction. The end of the conversion from the fourth output of block 10 through the element OR 22 records the additional subsurface code (ADC code; l () 7) in RAM 12, and then changes the state of the binary counter 23 to one and sets the following generator 26 itself. This completes the correction process and

After the switches 13 and 19 have been reset, the A / D device is ready for operation in real conditions. Other options for building block 17 are possible, providing other algorithms for obtaining exemplary stresses U, -.

The proposed device compares favorably with the known device in accuracy. The known device provides conversion of the input signal with a given accuracy only within the framework of those conditions under which the instrumental errors of the D / A converter 8 and the amplifier 6 differences are constant (as a rule, normal or laboratory conditions). Proposed setting45

50

55

It is connected to the third output of the control unit, the fourth output of which is connected to the control input of the N-bit output register, the high-end inputs of which are connected to the corresponding outputs of the arithmetic logic unit, and the outputs are output buses characterized in that in order to increase accuracy and increase speed, a digital adder, a random access memory, a switch, an OR element and a sample signal generating unit, the first output of which is connected to the first m data input switch, the second information input of which is an input bus and control input is combined with the first input unit and generating a model signal is a first control bus, reset input and recording a random access memory connected

The accuracy provides a given accuracy under any environmental conditions, since it is possible to adjust to their changes. This advantage is the stronger, the greater the number of bits of the analog-to-digital conversion.

gain formula

the control input is connected to the first output of the control location, the second output of which is connected to the control input of the memory register, the outputs of which are connected to the corresponding inputs of the first group of inputs of the arithmetic logic unit, information inputs which is combined with the input element of the

connected to the corresponding outputs of the analog-to-digital converter n higher bits, the output of the delay element is connected to the first input of the difference amplifier, the output of which is connected to the information input of the analog-digital converter junior

5 ™ Discharges that control the

0

five

0

five

It is connected to the third output of the control unit, the fourth output of which is connected to the control input of the N-bit output register, the high-end inputs of which are connected to the corresponding outputs of the arithmetic logic unit, and the outputs are output buses characterized in that in order to increase accuracy and increase speed, a digital adder, a random access memory, a switch, an OR element and a sample signal generating unit, the first output of which is connected to the first m data input switch, the second information input of which is an input bus and control input is combined with the first input unit and generating a model signal is a first control bus, reset input and recording a random access memory connected

respectively, to the second and third outputs of the exemplary signal shaping unit, the second and third inputs of which are the second and third control buses respectively, and the fourth input is connected to the fourth output of the control unit whose input is connected to the output of the OR element, yen with the fourth output of the sample signal formation unit, and the second input is located on the bus External trigger, the inputs N - the lower bits of the output L-times 15 register are combined with the first information inputs of the opera active memory device and connected to the corresponding Nn outputs of the lower digits of the digital adder, m inputs of the second group of inputs of the arithmetic logic unit are combined with the corresponding second information inputs of the random access memory and connected to the corresponding outputs of the m high bits of the digital totalizer, the first The Nn + m inputs of which are connected to the corresponding outputs of the analog-to-digital converter of the lower bits, the second inputs are connected to the corresponding outputs on then only memory, and third inputs connected to respective outputs

the output of the reference voltage source, the inputs of which are connected to the corresponding information outputs of the pulse counter, the zero input of which is combined with the first control input of the pulse generator, the first input of the OR element and connected to the output of the first switch, the first and second inputs of which are combined respectively with the first and second the inputs of the second and third switches and are respectively busses of logical zero and one; the output of the second key is connected to the first input of the AND element and is the second the output of the block, the third output of which is the output of the OR element, the second input of which is combined with the counting input of the pulse counter and is the fourth input of the block, the overflow output of the pulse counter is connected to the second input of the AND element, the output of which is connected to the installation input of 1 trigger, etc. My output is connected to the second control input of the generator, and the installation input to O is connected to the output of the third switch, the output of the generator is the fourth output of the block.

3, the apparatus according to claim 1, characterized in that the arithmetic logic unit is implemented in

random access memory, an AND element, an OR element, and a digital

the address inputs of which are connected to the corresponding outputs of the analog-to-digital converter and the higher bits, the second input of the difference amplifier is connected to the output of the digital-to-analog converter, the output of the switch is connected to the input of the delay line.

2, the apparatus according to claim 1, characterized in that the block forming exemplary signals is executed on the voltage source, the first, second and third switches, the OR element, the pulse counter, the AND element, the trigger and the pulse generator, the output of which is the fourth the output of the block, the first, second and third inputs of which are respectively the control inputs of the first, second and third switches, and the first output 40

45

50

55

cyNj iaTope-subtractor, the first information inputs of which are the corresponding inputs of the first group of inputs of the arithmetic logic unit, the input of the first bit of the second information inputs of the digital summator of the subtractor is the first input of the second group of inputs the arithmet of the co-logical device, the second-bit input of the second information inputs of the digital adder-subtractor l is connected to the output of the AND element, the first input of which is combined with the second input of the OR element, with the control input home digital adder-Comput bodies and is input to the second input of the second discharge group arifmetiko- logic device outputs are to torogo O rows corresponding digital adder-subtractor.

AND element, OR element and digital

The cyNj iaTope-subtractor, the first information inputs of which are the corresponding inputs of the first group of inputs of the arithmetic logic unit, the input of the first bit of the second information inputs of the digital totalizer subtractor is combined with the first input of the element ILI and is the first input of the second group of inputs of arithmetic -logical device, the second-bit input of the second information inputs of the digital adder-subtractor is connected to the output of the AND element, the first input of which is combined with the second input of the OR element, with the control they input of the digital adder-subtractor and is input to the second discharge of the second group of inputs arifmetiko- logic device, outputs of which are the respective outputs of the digital adder-subtractor.

;Table 2

Address Codes of additional-GALalogue equivalents in terms of GC. Ideal 1 1 soda I initial errors, mVmu level DAC 8, mV

128

I-001 4010

4-011

4100 4101 4110 "111

-0010 -0100

four

0110 -1000 -1010-1100-1110

-2 -4 -2 + (- 4) -6

ABOUT

-2 + (- 8) -10 -4 + (- 8) -12 -2 + (- 4) + (- 8) 14

256

128 + 256 384

512

128 + 512 640

256 + 512 768

128 + 256 + 512 896

Table 1

256

128 + 256 384

512

128 + 512 640

256 + 512 768

128 + 256 + 512 896

Claims (3)

Claim 1. An analog-to-digital conversion device containing an analog-to-digital converter η of higher digits, the information input of which is combined with the input of the delay element, and the control input is connected to the first output of the control unit, * the second output of which is connected to the control input of the memory register, the outputs of which are connected with the corresponding inputs of the first group of inputs of the arithmetic-logical device, and the information inputs are combined with the corresponding inputs of the digital-to-analog converter, constant the other device and are connected to the corresponding outputs of the analog-to-digital converter η of the upper digits, the output of the delay element is connected to the first input of the difference amplifier, the output of which is connected to the information input of the analog-to-digital converter of minor ¹ digits, the control input of which is connected to the third output of the unit control, the fourth output of which is connected to the control input of the N-bit output register, the inputs of the highest η bits of which are connected to the corresponding outputs of the arithmetic-logic of the device, and the outputs are output buses, characterized in that, in order to increase accuracy and increase speed, a digital adder, random access memory, switch, OR element, and a model signal generation unit are introduced into it, the first output of which is connected to the first information input a switch, the second information input of which is the input bus, and the control input is combined with the first input of the model signal generation block and is the first control bus, the inputs are reset The readings and records of random access memory are connected respectively to the second and third outputs of the model signal generating unit, the second and third inputs of which are the second and third control buses, respectively, and the fourth input is connected to the fourth output of the control unit, the input of which is connected to the output of the element OR, the first input of which is connected to the fourth output of the block for the formation of samples of signals, and the second input is an external trigger bus ”, the inputs N - η of the least significant bits of the output of the register are combined with the first information inputs of the operational memory • device and connected to the corresponding Ν-η outputs of the least significant bits of the digital adder, m inputs of the second group of inputs of the arithmetic logic device are combined with the corresponding second information inputs of the operational memory and connected to the corresponding outputs of the senior bits of the digital the adder, the first N-n + m inputs of which are connected to the corresponding outputs of the analog-to-digital converter low-order c, the second inputs are connected to the corresponding outputs of the read-only memory, and the third inputs are connected to the corresponding outputs of the random access memory, the address inputs of which are connected to the corresponding outputs of the analog-to-digital converter η high order, the second input of the difference amplifier is connected to the output of the digital-to-analog converter, the output of the switch connected to the input of the delay line. 2, device pop. 1, characterized in that the model signal generating unit is made on a reference voltage source, first, second and third switches, an OR element, a pulse counter, an And element, a trigger and a pulse generator, the output of which is the fourth output of the unit, the first, second and third inputs which are respectively the control inputs of the first, second and third switches, and the first output 10 to the output of the first switch, the first and second inputs of which are the output of the reference voltage source, the inputs of which are connected with the corresponding information outputs of the pulse counter, the zeroing input of which is combined with the first control input of the pulse generator, the first input of the OR element and the connector: combined with the first and second inputs of the second and third switches, respectively, and are logical zero and one buses, respectively, the output of the second key connected to the first input of the AND element and is the second output of the block, the third output of which is the output of the OR element, the second input of which is combined with the counting input of the count pulse counter and is the fourth input of the block, the overflow output of the pulse counter is connected to the second input of the element And, the output of which is under | keys to the input of the installation into a 1 ”trigger, the direct output of which is * connected to the second control input of the generator, and the input of the installation to 0” is connected to the output of the third switch; the generator output is the fourth output of the unit. 3. The device according to p. 1, characterized in that the arithmetic device is made on an AND element, an OR element, and a digital adder-subtractor, the first information inputs of which are the corresponding inputs of the first group of inputs of the arithmetic-logic device, the first discharge of the second information inputs of the digital adder subtractor is combined with the first input of the element OR> and is the first input of the second group of inputs of the arithmetic-logic device, the input of the second category of the second information inputs of digital the subtractor-subtractor is connected to the output of the AND element, the first input of which is combined with the second input of the OR element, with the control input of the digital adder-subtractor and is the input of the second discharge of the second group of inputs of the arithmetic device, the outputs of which are the corresponding outputs of the digital adder-subtractor. I 0 Table 1 Address Codes Codes of basic errors Analogue equivalents of errors, mV Matching the Ideal Level DAC8, mV +001 -011 -3 128 ¹ +010 +010 +2 256 +011 -001 -3 + 2 = -1 128 + 256 = 384 + 100 -100 . -4 512 + 101 -111 -3 + (- 4) = - 7 128 + 512 = 640 + 110 -010 +2 + (- 4) = - 2 256 + 512 = 768 + 111 -101 -3 + 2 + (- 4) = - 5 128 + 256 + 512 = 896 T a blitz 2 Address I Codes I Codes of additional errors I Analogue equivalents of errors, mV Compliance with the ideal DAC level of 8, mV +001 -0010 -2 128 4010 -0100 -4 256 4011 -0110 -2 + (- 4) = - 6 128 + 256 = 384 + 100 -1000 -8 512 4J1 -1010 -2 + (- 8) = - 10 128 + 512 = 640 + 110 -1100 -4 + (- 8) = - 12 256 + 512 = 768 + 111 “1110 -2 + (- 4) + (- 8) = 14 128 + 256 + 512 = 896 - "· < Figure 2