SU1418911A1 - Series-to-parallel code converter - Google Patents

Abstract

The invention relates to computing technology. The purpose of the invention is to extend the functionality of a serial to parallel converter. The serial to parallel converter contains a controller 1, a generator of 2 pulses, a transformation channel 3 containing a driver 4, a shift register 5, blocks 6-8 of the RAM, triggers 9-13, counters 14-17, elements OR 18 and 19, elements And 20-22, buffer registers 23, 24, frequency divider 25, multiplexer 26, bipolar-to-unipolar code converter 27, unicorn elements 28 and 29, and GFD 30, 31. 4 ill.

Description

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The invention relates to computer technology and is intended for use in information collection and processing systems using bipolar code-to-parallel conversion.

The goal of the acquisition is to expand the functionality of the device.

FIG. I shows a diagram of a serial to parallel converter; in fig. 2–4 are timing diagrams explaining the operation of the converter.

The serial to parallel converter includes (FIG. 1) controller 1, a pulse generator 2, a conversion channel 3 comprising a driver 4, a shift register 5, memory blocks 6–8 (BOP), triggers 9–13. counters 14-17, elements OR 1 8, 1 9, elements AND 20-22, buffer registers 23 and 24, divisor 25

controller on block B receives the resolution command (Fig. 2d). At the information input of block 8, the controller sets the recording attribute, and the immersG has a high potential if the address needs to be written down, and a low potential if not (Fig. 2e). Thus, the resolution command in block 8 of recording records information about the addresses that need to be written. After pre-recording by the Start command, which goes to the second input of channel 3 and then to the input of the element OR 18, the trigger 11 is set and the trigger 12 is reset (Fig. 3). A high potential from the direct output of the trigger 11 establishes the inhibitory potential or the reset input of the counter 15, the ac inverse output of the trigger 11 sets the enable potential at the reset input of the counter 16, i.e. this counter is activated by a signal from the direct output of trigger 12,

frequency, multiplexer 26 and converter 25 establishes the resolving potential of the recipient 27 of the bipolar code in the unison of the decoders 30 and 31 (Fig. 3g). i-OR, elements AND-OR 28 and 29, the input of the conversion channel is the input of converter 27. From its first output, a sequential unipolar code comes in, and from a second | go - a sequence of clock pulses. The 32-bit words of the unipolar code are separated by pauses. Shaper, finding a pause, forshiftyory 30 and 31.

The Converter operates as follows.

When the power is turned on, generator 2 is started up and a time countdown begins at the outputs of frequency divider 25. From the output of divider 25 at the data output

unit 7, connected to the input of the channel, synchronizes the pulses and, from its la 3, a code is set, the label of the

tilting time. The controller 1 according to the pre-recording command (Fig. 2a), which is fed to the input of channel 3, sets trigger 12 to the first to the state (Fig. 2b), at the output of trigger 12 a potential is set that is resolving for the first AND element element 28 and the first element AND element 29. By the same token, the second address input A of multiplexer 26, to which the controller's tenth output is connected, is switched to the output and thus data from the output of controller 1 is set at the address input of block 8. In addition, it is established the inhibitory potential at the gate inputs of the decoders 30 and 31. From the sixth control input of channel 3 connected to the fourth output of the controller via the AND-OR 29 element, a recording mode is set at the mode select input of block 8 (Fig. 2c). From the exit

output sends them to the counting input of the register 5 shift.

At the information input, the shift register receives a consecutive unipolar code, which, as the clock pulses go, exited at the output of the shift register 5 and more at the input of block 6. Eight data address bits from thirty-two I

the discharge word is sent to the first multi-texxor address input which is switched from the potential of the direct trigger 12 to the output set at the address input of the block 8. The inverse trigger output sets the raero potential at the input of the second element AND element 29. Upon the arrival of the thirty-second one, the pulse the input of the counter 14 (Fig. 3a), which comes from the generator 4, from its output of the input an impulse that sets three ger 10. In (Fig. 3B) the direct output of the trigger 10 is set high

the resolving potential is established on the decoders 30 and 31 (Fig. 3g).

The input of the conversion channel is the input of converter 27. From its first output, a consecutive unipolar code arrives, and from the second, | go - a sequence of clock pulses. The 32-bit words of the unipolar code are separated by pauses. The shaper, having found a pause, forms sync pulses and from its

output sends them to the counting input of the register 5 shift.

The sequential unipolar code enters the information input of the shift register 5, which, as the clock pulses arrive, is set at the output of the shift register 5 and then at the input of block 6. The eight data address bits from thirty-two I

of the bit word is sent to the first address input of the multi-hex detector 26, which by potential from the direct output of the trigger 12 switches to the output and is set at the address input of the block 8. The inverse output of the trigger 12 sets the same potential at the input of the second element AND element 29. On the arrival of the thirty second - po1 pulse to the input of the counter 14 (fig. Za), which comes from the imaging device 4, from its output a pulse arrives which sets the trigger 10. In (fig. 3B) the direct output of the trigger 10 is set to high

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the potential that arrives at the input of the element And 22. The second input of the element And 22 receives the frequency from the generator 2. Upon the arrival of the potential from the tenth output, the pulses start to flow to the input of the counter 16, from the output of the counter, to the input of the decoder 31 (Fig. Sv ) include his first exit. The impulse from the first output of the decoder sets the trigger 9. Direct output of the trigger 9 sets the potential that determines the recording mode at the inputs of the mode of blocks 6 and 7 (Fig. 3g). At their address inputs, the address is set from the output of the counter 17 (FIG. 3g), the physical address to the counter 17 is set from the seventh output of the controller connected to the ninth input of channel 3. The command for writing the address comes from the output of the controller connected to the tenth first channel input 3

The potential from the inverted output of the trigger 9 through the element 29 enters the input of the mode of the block 8 (Fig. Back), sets the read mode at this input, the second pulse from the counter 16 turns on the second output of the decoder 31 (fig. Sv). The impulse from the second output of the decoder, arriving at the input of the installations of the trigger 13, cocks it. The inverse output of the flip-flop 13 through the second element 28 is connected in recording mode to the input of the block 8. An impulse from the second output of the decoder forms the leading edge of the resolution signal for the block B (Fig. Зж). The third pulse from the output of the decoder 31 is fed to the second input of the element 20. By this time, the output of block 8 receives the sign of data recording, recorded previously in block 8. In case the sign of address writing is indicated by a high level, the pulse passes to the output of element 20 and then through element 19 on the resolution input of blocks 6 and 7 (Fig. 3.4). Thus, data is recorded in block 6 and the time of recording is block 7. The pulse from the fourth output of the decoder 31 is fed to the counting input +1 of the counter 17 and sets the next address at its output. The same pulse resets the flip-flop 13 and forms the falling edge of the resolution signal at the resolution B input of the block B (Fig. 3.c). The fifth pulse from counter 16 turns on the fifth output of the decoder 31. The pulse from this output goes to the reset input

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Sa trigger 10 and clears it (Fig. 3b).

At its direct output, a potential is formed that prohibits the passage of the frequency to the input of the element And 22. The recording process of the thirty-two-bit word is completed.

The schitgoan command arrives at the input of the element OR 18 from the ninth control output of the controller connected to the eleventh input of channel 3, and to the reset input of the trigger 11 and 12.

The potential from the direct output of the trigger 11 is fed to the reset input of counter 15 and enables it to work, while from the inverse output prohibits the operation of the counter 16. From the output of the OR 18 element, the pulse goes to the reset input of the trigger 12. As a result, the forward trigger output a potential is established which, upon entry to the gate of the decoders 30 and 31, allows their operation. In addition, the command to switch off switches on the inverse output of the trigger 9 (Fig. 4a). The potential from the inverse trigger output 9 g comes to the first input of the element 21 and allows the passage of the frequency from its second input to the output. The potential output of the trigger 9 for blocker 6 and 7 is set at the direct output of the trigger 9. From the output of the element 21, pulses are fed to the input of the counter 15. The first pulse from the output of this counter turns on the first output of the decoder 30 (Fig. 46). The impulse from this output enters the first input of the resolution of the buffer register 23 and connects sixteen output buses of this register to the input of the controller, simultaneously with the input of the element OR 19 and then from its output to the resolution inputs of blocks 6 and 7. The information recorded at installed on the counter 17 is installed on the inputs of blocks 6 and 7 and thus the sixteen first bits are connected to the input of the controller 1 (Fig. 4c).

The second pulse from counter 15 enables the second output of the decoder 30. The pulse from this output turns on the second enable input of the buffer register 23, connecting the second sixteen bits to the controller input and disconnecting

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the first. By the same impulse, the information is again read from blocks 6 and 7. The second sixteen bits of the thirty-two bit word arrive at the input of the controller. The third pulse from counter 15 turns on the third input of the decoder. The pulse from this output goes to the input of the resolution of the buffer register 24, connects sixteen of its output bits to the input of the controller I, disconnecting the remaining outputs of the buffer register 23. This same pulse from the output of block 19 counts the information from block 7 to the input of the roller.

The fourth pulse from the decoder 3 sets the output of the counter 17 to the following address. Fifth impulse from derailleur 30, arriving at the counting input of trigger 9, resets it. Thus, the reading of the word is completed.

Claims (1)

Formula and Acquisition The serial to parallel converter contains a controller, a pulse generator and in each of the conversion channels - the first RAM block, the first - the fourth trigger, the first and second counters, the AND elements, the OR elements and the first buffer register, the inverse output of the first trigger is connected to the first input of the first element AND, the second input of which is the first input of the conversion channel, the direct output of the second trigger is connected to the first input of the second element AND, the first input of the first element OR is W The first input of the conversion channel, the output of the pulse generator and the first output of the controller are connected to the first and second outputs of all conversion channels, respectively, characterized in that, in order to expand the functionality of the converter by providing the output information to be linked to the real-time scale, a divider is introduced into it frequencies and into each channel of the conversion - converter of the bipolar code into the unipolar, register pulse shaper, the second and third blocks of the RAM, the fifth trigger ep, third and fourth counters, AND-OR elements, de-encryptors and multiplexer, divider input 116 the frequency is connected to the output of the pulse generator, the output to the third inputs of the conversion channels, in which the output of the first element OR is connected to the reset input of the third trigger, the direct output of which is connected to the combined first inputs of the first elements AND of the first and second elements AND-OR, combined synchronous - Dami of the first and second registers and the switching input of the address inputs of the multiplexer, the output of the multiplexer is connected to the address input of the first a RAM block whose information input is the fourth input of the conversion channel, the output of the first RAM block is connected to the first input of the third AND element, the second inputs of the first AND elements of the first and second AND AND elements are respectively the fifth and sixth channel inputs conversion, the installation of the third trigger is the seventh input of the transformation channel, the inverse input of the third trigger is connected to the combined first inputs of the second And elements of the first and second I-IPI elements, the outputs of which are connected respectively to the first and second inputs of the mode selection of the first RAM block, the first output of the bipolar code conversion to unipol pt) 1J is connected to the first input of the pulse generator, the second output of the bipolar code to unipolar converter is connected to the second input of the pulse generator and the first input of the shift register, the second input of which is combined with the first input of the first counter and connected to the output of the pulse shaper, the first input of the third and the second input of the first counter combined with the third input of the shift register and are the eighth input of the conversion channel, the second and third inputs of the third counter are respectively the ninth and tenth inputs of the conversion channel, the output of the shift register is connected to the first address input of the multiplexer and the information input of the second memory block, the address input of which is combined with the address input of the third memory block and connected to the input of the third counter, the second input of the second element AND is connected to the first input of the channel The output, the second element And is connected to the first input of the second counter, the output of which is connected to the information input of the first decoder, the first, second, third outputs of which are connected respectively to the installation input of the first trigger, the installation input of the fourth trigger, the second input the decoder is connected to the reset input of the fourth trigger and the fourth input of the third counter, the fifth output of the decoder connected to the reset input of the second trigger-15 synchronization house of the first trigger. gera, the installation input of which is connected to the output of the first counter, the inverse output of the fourth trigger is connected to the second input of the second element AND of the first AND-OR element, the second 20 input of the second element AND the second element AND-OR is connected to the inverse output of the first trigger, reset inputs first and fifth trigger and second the input of the first element OR is combined by the 25th RAM block is the third input of the conversion channel; the output of the third RAM block is connected to the second input of the second buffer register, the input inverse outputs of the first trigger of the converter of the bipolar code converter to and are the eleventh input of the conversion channel, the setup input of the fifth trigger is connected to the first input of the first OR element, forward and dinene with the reset inputs of the fourth and second counters, the output of the second counter is connected to the information input of the second decoder, the output of the first element I is connected to the counting input of the fourth account of the scale, the first and second outputs of the second RAM block are connected respectively to the first and second inputs the first buffer register, the first and second outputs of which and the output of the second buffer register volume and the first and second outputs of the second decoder are connected respectively to the first and second inputs of the second OR element and the forward and fourth inputs of the first buffer register, the third output of the second decoder is connected to the third input of the second OR element, and the first input of the second the buffer register, the fourth and fifth outputs of the second decoder are connected respectively to the fifth input of the third counter and the input of the third element AND is connected to the fourth input of the second element OR, the output Which is connected to the first inputs of the mode selection of the second and third RAM blocks, the direct output of the first trigger is connected to the second inputs of the mode selection of the second and third RAM blocks, the information input is triple input of the transformation channel, the second address input of the multiplexer is the thirteenth input of the conversion channel, the outputs of all the conversion channels are combined and connected to the controller input, the second to the ninth outputs of which are connected to the fifth, eleventh, ninth, thirteenth, the fourth, tenth, eighth, and ninth inputs of the conversion channels, respectively. five  , 6  - .З