SU1191904A1 - Digital generator of periodic signals - Google Patents

Abstract

DIGITAL GENERATOR OF PERIODIC SIGNALS, which contains a pulse generator, a frequency divider, a code register, a counter, a code-analog converter, and the output is gene-. A pulse ramp is connected to the input of a frequency divider, the pre-installation input of which is connected to the generator input, which is also distinguished by the fact that, in order to increase speed, an address generation unit, a comparison circuit and a memory unit are inserted, the output of the frequency divider is connected to the counter input of the counter, the output of the counter is connected to the first input of the comparison circuit, the second input of which is connected to the output of the higher bits of the code scanner, the output of the lower order of which is connected to the control input. the formation of the code of the address generation unit, the output of the comparison circuit is connected to the combined reset input of the counter and the increment input of the address generation unit whose controlled output is connected to the address input of the memory unit whose output is connected to the code register input, the uncontrolled output of the address generation unit is connected to to the data input of the converter code analog, the 1 input of the polarity control of the signal of which is connected to the overflow output of the address generation unit, the output of the code analog converter is connected to generator output, the address generation block contains six AND elements, two groups of elements NOT, a group of elements OR, element NO, two triggers, two groups of elements AND, two keys, a reversible counter, and the output of the reversible counter is connected bitwise to the inputs of the elements NOT first and the second group, the first inputs of the AND elements of the first group, the inputs of the first element I and to the controlled output of the unit of the form (I will change the address, and the output of the first element I is connected to the input of the first key whose output is connected to the input S of the first trigger pa, whose R-input is combined with the first inputs of the second and third elements AND, and connected to the output of the fourth element; o, whose inputs are connected to the outputs of the elements NOT the first group, etc., O and inverse outputs of the first tri & They are connected to the first inputs of the fifth and sixth elements And, respectively, the second inputs of which are combined and connected to the increment input of the address generation unit, the output of the fifth element And connected to the forward count input of the reversible counter, the counting input of which is connected to the output of the sixth element And The input of the third element I is connected to the input of the second key, the output of which is connected to the S input of the second trigger, the R input of which is connected to the output

Description

the second element.and the second input of which is combined with the overflow output of the address generation unit and connected to the direct output of the second trigger, the inverse output of which is connected to the second input of the third AND element, the control input of the formation of the code of the address generation unit and the second the inputs of elements AND of the first group of outputs of elements NOT of the second group 1 4 are connected to the first inputs of elements AND of the second group, the second inputs of which are combined and connected to the output of the element NOT, the outputs of elements AND the second group ppy connected to first inputs of the OR elements of the group to the second inputs of which are connected the outputs of AND gates of the first group, the outputs of elements connected to rsi group uncontrolled emomu output generating unit, Adra ca. ,

one

The invention relates to automation and computer technology and can be used in control systems for electronic and electronic equipment, as well as in modeling stands for generating electrical signals that are periodic functions of time of various shapes.

The purpose of the invention is to increase the speed of the device at a high reproduction rate of the specified functions of time.

FIG. 1 shows a block diagram of a digital periodic signal generator; in fig. 2 is a diagram of an address generation unit.

The digital generator of periodic signals contains a generator of 1 pulses, a divider of 2 frequencies with an input 3 presetting a variable division factor, a counter 4 with a counting 5 and a fault 6 inputs, a comparison circuit 7, a code register 8 with the first 9 and second 10 outputs, block 11 TI, address generation unit 12 with the first 13, second 14 and third 15 outputs, the first to fourth 16-19 inputs, the converter code 20 with the first 21, second 22 inputs and output 23, which is one. temporarily is the output of a digital periodic signal generator.

The block of forming addresses 12 contains the following nodes: the first and second groups of elements are AND 24 and 25, respectively, the first and second groups of elements. NOT 26 and 27, respectively, the element is NOT 28, the first is the sixth element And 29-34, respectively, the reversible counter 35 with inputs

forward 36 and reverse counting 37, first trigger 38 with R input 39 and S input 40, second trigger 41 with R input 42 and S input 43, first and second keys 44 and 45 respectively, a group of elements OR 46.

A frequency divider 2 with input 3 for setting a variable division factor is a pre-set counter operating in cyclic mode. This counter generates a signal at its output whenever the number of pulses applied to its input becomes a multiple of the division factor. To do this, a fixed number is set on the trigger cells of the counter, which adds the division factor to the number 2, where n is the number of binary bits of the counter. The trigger cells of the counter are set to the required position via input 3. The frequency divider is made according to a known scheme.

The memory unit 11 is a set of addressable storage elements, which, together with the code register 8 and the reversible counter 35, form a reprogrammable read-only memory. In this case, the reversible counter 35, the contents of which is reproduced at the output 13, functions as an address register, and the code register 8 is the output data register t

The converter code-analog 20 allows the polarity of the signal at output 23 to be changed due to the fact that its 3 output element is a polarity switch controlled by an overflow signal from output 15 of block 12 to input 22. Block 12 at its output, 14 post pakitsiy on this output data in both forward and reverse binary code. To control the formation of the output of the 14 direct or reverse code of the reproduced number, one bit of each of the binary words stored in block 11 is used. The remaining bits of each of these words store the time interval code between the quantization nodes of the digital output signal. generator. When these words are entered into register 8, the contents of the bits displaying the time interval are reproduced at output 9 of this register, and the state of the discharge controlling the formation of the forward or reverse data code is fixed at output 10 of the same register. Digital periodic signal generator works as follows. The principle on which the operation of the digital generator, which forms a stage-shaped signal at its output 23, is based on the fact that the positional binary codes at the outputs 13 and 14 of unit 12 receive single increments at times that correspond to moments uniform in the quantum level. reproduced function. At the same time, at the output 13 of the block 12, the codes of the addresses of the memory cells of the block 1 are formed in which the codes of the time intervals between the quantization nodes of the output signal representing the periodic time function ng output 23 are stored. Simultaneously with the formation of a code at the output 13 of one or another code, the code equal to or opposite to it is formed at step 14, which at each current time instant determines the absolute value of the reproducible function. The digital periodic signal generator operates in two modes determined by the setting of the reversible counter 35: forward and substituted. In the forward mode, the reversible counter 35 conducts a continuous count of pulses acting on the input 04. 4-16, successively changing its contents from zero to the maximum possible value, repeating these actions many times. The combined operation of the reversible counter 35 realizes a continuous alternation of the forward pulse counting acting on the input 16 with a reverse one. In this case, the contents of the reversing counter 35 vary cyclically from zero to the maximum value and from there to zero, to ensure proper functioning of the digital periodic generator signals must be configured to play a specific function at a given frequency. This setting is to perform the following operations. Recording information into the memory cells of block 1 I. This operation is carried out according to a well-known data entry technology in reprogrammable permanent memory devices. Setting the frequency division factor on the 2 frequency divider. This operation is performed to provide a predetermined reproduction frequency of a known function. The key 44 is installed in one of the two fixed positions for organizing direct or combined operation of the reversible counter 35. With the open position of the key 44, the direct operating mode with closed is realized - combined. The key 45 is installed in one of two fixed positions to control the polarity of the output of the digital oscillator. When the key 45 is turned off, the output signal polarity is constant, while the key 45 is closed, the output signal polarity changes periodically. In this case, the change in the sign of the output signal occurs when the contents of counter 35 are zero, and the time between these moments depends from the state of the key 44, with the key open 44, this time is equal to the duration of the cycle of the direct mode, and when closed, the combined mode. The digital oscillator of the periodic signals starts at zero content of the counter 4 and the reversible counter 35 after performing the tuning operations. Wherein

at output 13, a zero code is fixed, and the contents of the zero cell: block 11, which determines the time before the first quantization of the output signal, is output to register 8. Triggering pulse generator 1 provides signals to count input 5 of counter 4 with a frequency equal to the ratio of the frequency of the pulse generator 1 to the frequency division factor set on divider 2

At the moment of coincidence of the contents of the counter 4 with the code at the output 9 of the register 8, the circuit 7 generates a pulse acting on the fault input 6 of the counter 4 and on the input of the increment 16 of the block 12. As a result, the contents of the counter 4 again become equal to zero, and at the output 13 of the block 12 . a code is set equal to one, which results in entering the register 8 of the contents of the first cell of block 1I.

Further, this process is repeated many times with the difference that the time between subsequent pulses on the outflow of circuit 7 is determined by the contents of the other memory cells of block 11.

At the same time, the addresses of the excited memory cells of block 11 change in accordance with the assigned mode of operation of the reversible counter 35, since its content is reproduced at output 13.

The forward mode of operation of the reversing counter 35 is determined by the open state of the key 44. In this case, when the reversing counter 35 has zero initial state, the signals of the direct outputs of all bits of this counter pass through the corresponding elements of the HE group 26, causing the signal a high level at the output of the element 32. This signal, arriving at the R input of the trigger 38, puts it in the zero state. Since the circuit affecting the S input 40 of this trigger is open with key 44, then the trigger 38 remains in the zero position. Therefore, the trigger 38 in this case continuously acts on one of the inputs of the And 33 and 34 elements by the low and high signal signals, respectively. The pulses, which at the same time affect the input 16 increments, over the element And 33, pass to the input 36 of the forward count of the reversible counter 35, causing a cyclical change in the contents of this counter from zero to the maximum. Accordingly, the cells of block 11 are addressed.

Combined operation of the reversible counter 35 Occurs when the key is closed 44. In this case, the reversing counter 35 sequentially implements a direct and reverse counting of the pulses entering input 16. Since the key 44 is closed, then by the end of the direct counting, when reversing the counter 35 is set to the maximum number encoded by units in all bits, a high level signal arrives at S-input 40, which occurs at the output of the I 29 element. At the same time, the R-input 39 of the flip-flop 38 from the I 32 element comes from drove the low level. As a result, the trigger 38 goes from the zero state to the normal state, and the signals at its outputs change their polarity. Consequently, the pulses perceived by the input 16 of the increment in this case excite the input 37 of the reverse counting of the reversible counter 35, arriving at it through the element 34. The counter 35 sequentially reduces its contents to zero. The zero content of the reversible counter 35 causes a change in the polarity of the signals at the inputs 39 and 40 of the flip-flop 38, which changes its state and leads to the repetition of the cycle characterizing the combined mode.

In the combined operation mode of the revisive counter 35, the excited addresses of the memory cells of the block 11 are cyclically repeated, and within each cycle they change sequentially from zero to maximum and then from maximum to zero. Such addressing of the memory cells in combination with the possibility of changing the polarity of the signal at the output of the generator 23 makes it possible to generate signals that reproduce even and odd symmetric functions, for example harmonic ones. At the same time, the volume of used storage elements for block 11 is minimized.

Simultaneously with the code change at step 13, which is performed incrementally, the signal at output 14 also changes incrementally. At the same time, a positional binary code is generated at output 14 equal to or inverse to the output code 13. For example, to generate relaxation oscillations and reproducing functions that have on the direct cycle interval two associated monotonic portions with different signs of the derivative. The control of the formation of a code at the output 14 is performed on a binary signal from the output 10 of the register 8 to the input 17 of the control of the formation of the code of block 12, and is carried out as follows. The code formed by the reversible counter 35 and reproduced at the output 13 also goes to the group of elements And 24. Group 25 perceives this code bitwise, using one of the inputs of each of its own element I. Thanks to this, at a high signal level at the input 17, which affects the other inputs of elements AND of group 24, the outputs of the latter duplicate the contents of counter 35. At the same time, low level signals are generated at the outputs of the group of elements AND 25, since one of the inputs of each element of this block is affected by a low signal who level; This low level signal comes from the output of the NOT 28 element, which inverts the high level signal acting on the input 17. In this case, therefore, the group of 46 OR elements transmits the state of AND elements 24 that reproduce the contents of the reversible counter 35 to Exit 14 , ensures the coincidence of codes at outputs 13 and 14. A low signal level at input 17 leads to the formation of a code at output 14, back to code at output 13 This is due to the fact that, on the one hand, the signal at low level of input 17 affects items And the group 24, leads to the formation of low level signals on the extrusions of the elements of this group, on the other hand, the high level signal formed at the output of the element NOT 28 enters the input of each element AND of group 25, due to which this group of elements duplicates at the outputs of its elements, the output signals of the elements of group 27. Since the reversible counter 35 is bitwise connected to the elements NOT group 5, the output of the latter, and hence the output of the -25 group, displays the code reversed by the reversible fixed counter 35. As a result, The total addition of binary signals of group 25 and low level signals of group 24, performed by the elements of OR group .46, the output of the latter is formed by a code reversed by the fixed reversible counter 35 and the code at output 13. The polarity of the periodic signal: output 23 of the digital oscillator is determined by the signal level at the output 15 of the flip-flop 41. The signal level at the output 15 is controlled by the key 45. With kg 45 open, the digital periodic signal generator operates with a constant output signal. This is because, in the initial state, the reversible counter 35, when its content is zero, a high level signal appears at the output of the AND 32 element. If in this case the trigger 41 is in the single state, then the signal from its Woro output 5, acting together with the high signal level of the element 32 on the inputs of the element 30, causes a high signal at the output of this element. This signal, driving the R-input 42 of the flip-flop 41, brings it to the zero state. If, at the initial position of the reversible counter 35, the trigger 41 is in the zero state, then it does not undergo a change. The zero state of the flip-flop 41 when the key 45 is open, and hence the polarity of the signal at the output 23 remains unchanged, since the open key 45 eliminates any impact on the S input 43 of the flip-flop 41. With the closed key 45 the trigger state 41 and, therefore, the polarity of the signal at the output 23 changes whenever the contents of the reversible counter 35 take a zero value, the overflow signal of the block 12 is received. This is because the cross-feedbacks of the forward and reverse output of the trigger 41 with its inputs 42 and 43, organized ated by means of AND gates 30 and 31 are turned on simultaneously each time when the output member 32 occurs and high level signal defined by the zero state of the reversible counter 35, In this case, the time between the moments pere1 410. the key switch 41 is determined by the duration of the cycle of the direct mode of operation of the reversible counter35 in case the key 44 is open, and with the key 44 closed, the duration of the cycle of the combined mode of operation of this counter.

W d

J

0

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22

21/4

15

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sixteen

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figure 1

Claims (1)

DIGITAL PERIODIC SIGNAL GENERATOR, comprising a pulse generator, a frequency divider, a code register, a counter, a code-analog converter, the pulse generator output being connected to an input of a frequency divider, the preset input of which is connected to the generator input, characterized in that, in order to increase the speed , an address generation unit, a comparison circuit and a memory unit are introduced into it, the output of the frequency divider being connected to the counter input of the counter, the output of the counter connected to the first input of the comparison circuit, the second input of which is connected to the high-order output of the code register, the low-order output of which is connected to the control input. by generating the code of the address generation unit, the output of the comparison circuit is connected to the combined counter reset input and the increment input of the address generation unit, the controlled output of which is connected to the address input of the memory unit, the output of which is connected to the code register input, the uncontrolled output of the address generation unit is connected to the data input of the converter code — analogue, the signal polarity control input of which is connected to the overflow output of the address generation unit, the output of the code — analog converter is connected to the output generator, and the address generation block contains six AND elements, two groups of NOT elements, a group of OR elements, an NOT element, two triggers, two groups of AND elements, two keys, a reversible counter, and the output of the reversible counter is connected bitwise to the inputs of the NOT elements of the first and the second group, the first inputs of the elements And the first group, the inputs of the first element And and to the controlled output of the address generation unit, and the output of the first element And is connected to the input of the first key, the output of which is connected to input S of the first trigger, R-input cat Orogo is combined with the first inputs of the second and third elements And and connected to the output of the fourth element And, the inputs of which are connected to the outputs of the elements NOT of the first group, the direct and inverse outputs of the first trigger are connected to the first inputs of the fifth and sixth elements And, respectively, the second inputs of which combined and connected to the input of the increment of the address generation unit, the output of the fifth element And is connected to the input of the direct count of the reverse counter, the input of the counting of which is connected to the output of the sixth element And, the third input about the AND element is connected to the input of the second key, the output of which is connected to the S input of the second trigger, the R-input of which is connected to the output of the second element. And, the second input of which is combined with the overflow output of the address generation unit and is connected to the direct output of the second trigger, inverse the output of which is connected to the second input of the third AND element, the input for controlling the formation of the code of the address forming unit is connected to the input of the NOT element and the second inputs of the AND elements of the first group, the outputs of the NOT elements of the second group are connected to the first odes of elements AND of the second group, the second inputs of which are combined and connected to the output of the element NOT, the outputs of the elements AND of the second group are connected to the first inputs of the elements OR of the group, the outputs of the elements of the first group are connected to the second inputs of the outputs of the elements OR of the group are connected to the uncontrolled output of the block formation. address sa. ,