SU1554126A2 - Device for pulse delay and shaping - Google Patents

Abstract

The invention can be used in automation systems and is an improvement of the device according to the main author of the USSR USSR N 1345327. The purpose of the invention is to expand the functionality by interrupting the execution of a regular command at a desired point in time, as well as execution of priority commands. This goal is achieved by introducing into the device two additional switches 10 and 11, buses 15, accelerated transition, tires 16 interrupts. In addition, the device includes a controlled clock generator 1, a pulse counter 2, two triggers 3 and 8, two elements OR 4 and 5, a driver 6 pulses, shift register 7, switch 9, input bus 12, reset bus 13 , tires 14, assignment of codes, output busses 17. Introduced elements provide the ability to interrupt the program at the required time by sending signals to the corresponding interrupt buses 16 before the signal from the corresponding fast transition from the buses 15. Moreover, in the proposed device, it is possible to execute a command from priority signals from a system occupying a higher level of hierarchy. 2 Il.

Description

14)

This goal is achieved by introducing into the device two additional switches 10 and I, the bus 15 of the accelerated transition, the bus 16 interrupt. In addition, the device includes a controlled generator of 1 clock pulses, a counter of 2 pulses, two triggers 3 and 8, two elements OR 4 and 5, a driver of 6 pulses, shift register 7, switch 9, input bus 12, bus 13 reset, bus 14, specifying codes, output bus 17. The input elements provide the ability to interrupt the program at the required time by sending signals to the corresponding bus 16 interrupts until a signal appears from the corresponding fast transition from bus 15. Moreover, in the proposed device, it is possible to execute a command from priority signals from a system occupying a higher level of hierarchy. 2 Il.

The invention relates to a pulse technique, can be used in automation systems and is an improvement of the device according to the author. St. No. 1345327.

The purpose of the invention is to expand the functionality by ensuring the interruption of the execution of the next command at the required time, as well as the ability to execute priority commands.

The goal is achieved by the fact that the device additionally includes accelerated transition buses, two additional switches, interrupt buses, and new connections.

FIG. 1 is a functional diagram of a delay and pulse generation device; in fig. 2 - implementation of a controlled clock generator is possible.

The device for delaying and shaping pulses contains a controlled oscillator 1 clock pulses, a pulse counter 2, the first trigger 3, the first 4 and second 5 elements OR, the driver 6 pulses, the shift register 7, the second trigger 8, the first 9, the second 10 and the third 11 switches: input bus 12, reset bus 13, set code bus 14, bus 15 interrupt bus 16, and output bus 1.7. The output of the controlled oscillator 1 clock pulses is connected to the clock input of the pulse 2 pulses, the transfer output

through which the pulse shaper 6 is connected to one of the inputs of the first element OR 4, the other input of which is connected to the input bus 12 and one of the inputs of the first trigger

five

0

five

about

Q 5

3 connected by another input to the reset bus 13 and to the zeroing input of the shift register 7, the synchronization input of which is associated with the output of the first element OR 4 and with one of the inputs of the second element OR 5 connected by another input to the output of the first trigger 3. The output of the second element OR 5 is connected to the resolution input of the pulse counter 2, the D inputs of which are connected to the outputs of the first switch 9 connected by the first group of inputs to the outputs of the shift register 7 and to the first groups of inputs of the second 10 and third 11 switches. The output of the first bit of register 7 is connected to one of the inputs of the second trigger 8, which is connected to the D input of the shift register 7. The reset bus 13 is connected to the second input of the second trigger 8. The output of the second switch 10 is connected to one of the inputs of the controlled clock generator 1, the other input of which is connected to the output of the third switch 11. The task setting buses 14 are connected to the second group of inputs of the first switch 9 Output bus 1.7 connected to the outputs of the register 7 shift. The bus 15 accelerated transition is connected to the second group of inputs of the third switch 11, and the bus 16 interrupt are connected to the second group of inputs of the second switch 10.,

FIG. 2 shows the possible implementation of a controlled oscillator 1 clock pulses, which consists of the element HE 18, the generator 19 pulses, frequency divider 20, element 2I-ZI-2ILI 21 and element HE 22.

5I 5

The delay device and the formation of pulses works as follows

The voltage impulse coming through the reset bus 13 sets the shift register 7 to the zero state and the first 3 and second 8 flip-flops to one states. From the output of the first trigger 3, the logical 1 signal through the second element OR 5 is fed to the resolution enable input of 2 pulses. According to this signal, information received via the D-inputs of pulse counter 2 is rewritten into the output bits of counter 2. Because the outputs of shift register 7 generate logical signals O, then the outputs of the first switch 9 are independent of the code on the task buses 14 codes formed signalg .: logical O. Therefore, at the output of the transfer of the counter 2 pulses set to zero. As a counter of 2 pulses, a counter working on subtraction is used. At the outputs of the second 10 and third 1I switches, logical O1 signals are generated and the controlled clock generator 1 produces pulses of nominal frequency. However, the counting of pulses by the counter 2 is not performed, since a single signal is generated at its resolution input.

The device can operate in several modes. In the case of the absence of signals on the tires 15 of the accelerated transfer in the tires 16 interrupt the device operates as follows. When the input pulse arrives on the input signal bus 12, the first trigger 3 overturns and a logic signal O is set at its output, however, the reversible counter 2 pulses does not start counting the pulses, because the input pulse passes through the first 4 and second 5 elements OR to the counter enable input. The leading edge of the input pulse through the first element OR 4 at the first digit of the shift register 7 is a signal of logical 1, since a single signal is formed at the D input of the shift register 7. The logical 1 signal from the output of the first bit of the shift register 7 sets the second trigger 8 to the zero state and simultaneously goes to the first switch 9. Thus, from the bus 14 to set the codes the delay setting code

26

the first pulse through the first switch 9 is fed to the D-inputs of the counter 2 pulses. During the duration of the input pulse, the delay code of the first pulse, formed at the D inputs of the counter, is rewritten into the output bits of the reversible counter 2 pulses, and the signal of the logical 1 is set at the transfer output of the counter.

At the end of the input pulse, on the resolution input of the pulse counter 2, a logical signal 0 | and the pulse counter begins to work on the subtraction, i.e. The delay code for the first pulse starts. When the specified delay time of the first pulse at the outputs of the bits of the counter 2 pulses is reached, logic O signals are set and a voltage drop from 1 to O is formed at the transfer output of the counter. By this voltage drop, the driver 6 produces a voltage pulse, the duration of which should be less than the period clock frequency of the controlled oscillator 1. But the leading edge of this pulse records the unit from the first bit of the shift register 7 to the second bit, thereby forming the leading edge of the first delayed pulse on the first output bus 17. In this case, a zero signal is set at the first digit of the shift register 7.

The D-inputs of the pulse counter 2 through the first switch 9 receives the code of the duration of the first pulse from the bus 14 task codes. The voltage pulse from the output of the imaging unit 6 through the first 4 and second 5 elements OR is fed to the resolution input of the pulse counter 2 and rewrites the code of the first pulse duration from the D inputs to the output bits of the pulse counter 2, while the output of the counter transfer is set to one signal. At the end of the voltage pulse from the output of the imaging unit 6, the pulse counter 2 begins to write off the code of the duration of the first output pulse. By installing three zero signals at all bits of the counter, at the transfer output of the counter, a voltage drop from one to zero is generated and the driver of 6 pulses produces a voltage pulse,

the leading edge of which rewrites the unit from the second bit of the register 7 shift to the third. Thus, at the output of the second bit of the shift register 7, the falling edge of the delayed pulse is formed.

Similarly, the formation of subsequent output pulses. Thus, setting the code values on the code setting buses 14, a sequence of delayed pulses of different duration can be formed at any time during a work cycle. If a signal appears on the corresponding interrupt bus during a work cycle, a single signal is generated at the output of the second switch 10 The oscillator stops generating nominal frequency clock pulses, and the cycle of the delay device and pulse shaping is interrupted.

When a signal appears on the corresponding bus 15 of the accelerated transition, a single signal is generated at the output of the third switch 11, which is fed to the input of a controlled oscillator 1 clock pulses. This signal prevents the generation of clock pulses of a nominal frequency and allows the formation of clock pulses of increased frequency. The information recorded in pulse counter 2 is written off by high frequency pulses, shaper 6 generates a voltage pulse, which rewrites the output signal logical 1 of shift register 7 to the next discharge. In addition to the fact that this signal connects the new code from the buses 14, which assign codes to the counter 2 pulses, it prohibits the passage of signals through the switches 10 and 11 from the corresponding buses 16 interrupts and the buses 15 of the rapid transition. The outputs of the switches 10 and 11 are set to logic O and the controlled oscillator 1 again generates clocks of nominal frequency.

If a signal is formed on the corresponding bus 15 of the accelerated transition (in the absence of signals on the interrupt buses), the controlled oscillator 1 generates pulses of increased frequency, i.e. the signals on the fast track tires are prioritized. Further work process

0

five

0

five

0

five

0

five

similar to the specified. If it is necessary to complete the operation cycle of the device, the output of the last bit of the shift register 7 must be connected to the S-input of the first trigger 3 (in Fig. 1 shown by a dotted line).

The controlled clock generator 1 can be made in various ways: it can consist of two generators of different frequency and logic circuits, it can contain one generator with a frequency divider, etc. FIG. 2 shows one of the possible implementations of the controlled oscillator 1 clock pulses. When the input element HE 18 (from switch 10 output) of logical 1 is prohibited, the pulse from frequency divider 20 is not transmitted to the output of controlled oscillator 1. If a logical signal is received from the input of switch I, then high frequency pulses from generator 19 are generated controlled oscillator output 1. If a logical |: 0 signal is generated at the output of switch 10 (at the input of the HE element 18) and in it, the switch 1 generates a sipple of logical 1, then a bullet signal is set at the output of the HE element 22 that prevents the passage of pulses from the frequency divider 20 At the same time, the passage of impulses from generator 19 is permitted. Switches 10 and 11 can also be made in various ways, on logical elements 2I-2I -...- 2I- -PIL, where n is the number of elements 2I. Moreover, one of the inputs of each element 2I is connected to the corresponding interrupt bus (accelerated transition), and the other is connected to the corresponding output bit of the shift register 7.

Thus, in the device there is the possibility of interrupting the work cycle at the required time, the possibility of continuing the cycle from the next clock cycle, as well as the possibility of executing priority commands that come from the buses of the rapid transition. The introduction of new elements and connections allows to expand the functionality of the delay and pulse generation device. The device can be used in particular when controlling various technological processes and provides additional possibilities for interrupting the execution of a regular operation or speeding up the corresponding operation according to signals from another system occupying a higher level of hierarchy.

Claims (1)

Invention Formula ten The device for delaying and shaping pulses according to autor.st. No. 1345327, characterized in that, in order to expand the Functional capabilities by ensuring the interruption of the execution of the next command at the required time, as well as the output of 18 L CbsodiT yy 0 the ability to execute priority commands, accelerated transition buses, two additional commutators and interrupt buses connected to the first group of inputs of the first additional switch connected to the first input of the controlled clock generator connected to the output of the second additional switch by the second input , the first group of inputs of which is connected to the buses of the accelerated transition, and the second groups of inputs of both additional switches are connected to the codes of the shift register ha to Z1 kg Figg