SU1499439A1 - Programmable shaper of time intervals - Google Patents

Abstract

The invention can be used in information-measuring equipment and in various microprocessor-based electronic equipment. The purpose of the invention is to expand the range of time intervals to be formed. This is achieved by introducing trigger 4, which summarizes the three time intervals generated by programmable timers 2 and 3. The operation of these timers is controlled by introducing the element OR-NOT 5, D-flip-flops 6 and 7, the element OR 8. The device also contains a divider 1 frequency. 2 Il.

Description

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The invention relates to a pulse and information-measuring technique and can be used in various microprocessor-based electronic equipment.

The aim of the invention is to expand the range of time intervals to be formed while ensuring a given shaping accuracy (discreteness).

FIG. 1 shows a functional diagram of a programmable time interval generator; in fig. 2 - time diagrams that show his work.

The programmable time interval generator contains a frequency divider 1, programmable timers 2 and 3, D-flip-flop 4, element OR-NOT 5, D-flip-flops 6 .and 7. element OR 8, bus 9 Reset, information control bus 10, bus 11 Start, input bus 12 pulse sequence, outputs 13 and 14.

The input bus 12 of the pulse sequence is connected to the clock input of the programmable timer 3 and the input of the frequency divider 1, the output of which is connected to the clock input of the programmable timer 2. The bus 9 Reset is connected to the R inputs of the D-triggers 4, 6, 7. Hchina 11 Start is connected with the first input of the CHI- element. NOT 5, the output of which is connected to the gate input of the programmable timer 2. The output of which is connected to the clock input of the D-flip-flop 6, the gate input of the programmable timer 3, the first input of the element OR 8 and the clock input of the D-flip-flop 4, the output of which is output 13 of the device D-flip-flop 4 is connected to the output of the element OR 8, and D- input - to the inverse output of D-flip-flop 7. The direct code of D-flip-flop 7 is connected to the second input of the element OR 8 and the second input of the element OR-NOT 5, and clock input - with the output of programmable timer 3, R-input divides l

1 frequency and output 14 devices. Information, address and control programmable timers

2 and 3 are connected to the information control bus 10 No. 1 of the process system. On the D-input of the D-flip-flop 6, the level is a logical zero, on the D-input of the D-flip-flop 7 - the level of a logical one.

wear

The shaper works as follows.

In the initial state, the D-flip-flops 4, 6 and 7 are reset with a short-term pulse through the bus 9 Reset and the level of logic zero is set at their forward direct outputs, and the level of logic one is set at the inverse output of O-trigger 7. Frequency divider 1 is in the pulse counting mode of an external oscillator. Programmable timers 2 and 3 are programmed using information, address and control buses 10 of the microprocessor system, working in the monoviraph mode, the coefficients K, and K that enter them, which determine the duration of the output pulse of the device, are determined from

(K + K

g

1) +

(one)

Where

0 0, c t

T A4

0

five

the duration of the time interval being formed, the period of the frequency of the external pulse generator, and the coefficient (1), the dividing agent of the frequency divider 1 /

K, the numbers stored in the counter of the programmable timer 2 to form the first and third pulses of the device

To the number entered in the counter of the programmable timer 3 to form the second pulse of the device.

There are two possible programming options for the programmable timer 2,

At the first, the value of the coefficient entered into the timer counter does not change during device operation, and at the second timer the coefficient K is initially entered into the counter, and then during the formation of the second pulse of the device K is replaced (programmed) with K. The microprocessor system receives a signal about the readiness of the driver to receive the coefficient Kj from the output 14 of the device. If during the operation of the programmable timer 3 the reprogramming of the programmable timer 2 is not performed, then K K

 TO

expression (1) takes the form

That (cd,

(2K + 1) + K, + 1). (2)

Operation of the device begins on arrival via bus 11. Starting the working (positive) pulse front to the first input of the element OR NOT 5 (Fig. 2c). Negative difference from the output of the element OR NOT 5 (fig.2g) translates to S-INPUT P- the trigger 6 is in the unit state (Fig. 2e), as a result of which a high logic level is set at the gate input of the programmable timer 2. At the moment of arrival of the first working (negative) pulse front from the output of the frequency divider 1 (Fig. 26) to the clock input of the programmable timer 2, a low logic level is set at its output (Fig. 2e), which is fed to the first input of the element OR 8. Since the second input of the element OR 8 is fed a low logic level from the direct output of D-flip-flop 7 (Fig. 2d), then the output of the OR-8 element is set to a logic zero level (Fig. 2k), which converts the D-flip-flop 4 to the unit state on S-BOX (Fig. 2l). Upon completion of the formation of the first pulse at the output of programmable timer 2, a high logic level is established and the positive differential arriving at the gating input of programmable timer 3 is allowed to form the second one.

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timer 2 is disabled, becomes

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ten

20 it is possible to reprogram it with a microprocessor; oh system (if necessary), i.e. replacement of the coefficient K by the coefficient K ,,. To this end, device output 14 can be connected to the interrupt request inputs of the microprocessor system.

During the formation of the second pulse at the output of the programmable timer 3, the low logic level is established. 1, which is fed to the R-input of the frequency divider 1 and sets it to the initial (zero) state (Fig. 25). Thus, when restarting the programmable timer 2 (the beginning of the formation of the third pulse), the duration of its switching on is constant and equal to the pulse following period from the output of frequency divider 1 (Fig. 2e).

At the end of the second pulse, a logical unit is written to the D-flip-flop 7 at the C-input by a positive differential from the output of the programmable timer 3, which is set at the direct output of the D-flip-flop 7 (Fig. 2h), and its inverse output - the level logical zero (Fig. 2i). From the direct output of the D-flip-flop 7, the level of the logical unit is applied to the second input of the element OR-NOT 5, the output of which again sets the level of the logical zero (Fig. 2d), with the result that the D-flip-flop 6 repeatedly resets. walks in a single state on the S-input control (Fig. 2e). Then the cycle repeats.

thirty

35

The device’s second pulse. In addition to the 40 Works of programmable timer 2, the output of the element OR 8 is set to the output of which a third

impulse device (Fig. 2e), with the leading edge of the generated pulse

the level of the logical unit is applied, which is fed to the S input of the D trigger 4 and enables the trigger

delayed relative to the rear

on the C input. The formation of the second pulse, the generated pulse of the device, begins on a pre-programmed timer 3, at a high rate.

running on the clock input of the programmable timer 3 through the input bus 12 of the working (negative) front of the frequency of the external generator, while the leading edge of the generated pulse is delayed relative to the rear edge of the pulse formed by the programmed 1 timer 2, the value of TD, which is included in the total duration the resulting time interval (Fig. 2g).

Since during the operation of the programmable timer 3 programmable

50

55

Td Cd (which is included in the total duration of the received time interval. At the end of the third pulse, the positive difference from the output of programmable timer 2 to D-flip-flop 4 is entered into a logical zero from the C-input. Thus, at D-flip-flop 4 (output 13 of the device) a time interval of duration with b is formed in accordance with the expression (1) and (2) (fig. 2l) as the sum of the time intervals determined by: the duration of the first pulse

delayed relative to the rear

TO

0

five

Td Cd (which is included in the total duration of the received time interval. At the end of the third pulse, the positive difference from the output of programmable timer 2 to D-flip-flop 4 is entered into a logical zero from the C-input. Thus, at the output of D-flip-flop 4 (output 13 devices) a time interval with a duration of c is formed in accordance with the expression (1) and (2) (Fig. 2l) as the sum of the time intervals determined by: the duration of the first impulse.

Editor N.Lazarenko

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Compiled by Yu.Sibir to

Tehred A. Kravchuk Proofreader M.Samborsk

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Claims (1)

Claim A programmable time slot driver comprising a frequency divider, the output of which is connected to the clock input of the first programmable timer, the output of which is connected to the gate input of the second programmable timer, whose clock input is connected to the input of the frequency divider, information, address and control inputs of the first and second programmable timers with an information-control bus, the first D-flip-flop, the installation input in O ”of which is connected to the Reset bus, characterized in that, in order to expand the range of the generated time intervals while ensuring the given discreteness, it is entered element 5 OR, the element OR is NOT, the second and third D-triggers, while the Start bus is connected to the first input of the OR-NOT element, the output of which is connected to the S-input the second D-trigger, the D-input of which is connected to a logic zero source, and the clock input is connected to the clock input of the first D trigger, the first input of the OR element and the output of the first programmable 15 timer, the output of the second D-trigger is connected to the gate input of the first programmer timer, the Reset bus is connected to the R-inputs from the first to the third D-flip-flops, the clock 20 input of the third D-flip-flop is connected to the output of the second programmable timer and the R-input of the frequency divider, the D-input of the third D-flip-flop is connected to the source of the logical unit , the inverse version 25 output of the third D-trigger is connected to the D-input of the first D-trigger, and the direct output is connected to the second inputs of the OR-NOT and OR elements, the output of the OR element is connected to the S-input 30 of the first D-trigger. about δ ί g d e w o to i