SU1434545A1 - Code-to-time interval converter - Google Patents

Abstract

The invention relates to computing and can be used in instrumentation. The purpose of the invention is to increase the speed and expansion of the field of application by operating in a wider range of clock frequencies and control signals. The pulse on bus 1 of the initial installation is reset to the initial state. / A pulse on bus 2 starts a 3-pulse generator, starting the formation of a clock frequency. On the forward front of the first clock pulse, the information is recorded. In the counter 8 pulses, and the trigger b is set to 1. On the falling edge of the clock pulse, the trigger 5 is set to O and thereby blocks the NAND element 4. On the falling edge of the clock pulses arriving at The subtracting input of the counter 8 through the open element AND-HE 7 is counted down. Simultaneously with the pulse that triggers the counter triggers from state O to state 1, a pulse is formed at the output of counter 8, which ends the time interval, and the device returns to its initial state before the next trigger pulse arrives. 2 Il. i cl c

Description

"By Jiff

SL

4 SP

114

 The invention relates to computing and can be used in instrumentation.

The purpose of the invention is to increase the speed and expand the range of application of the converter due to the possibility of operating in a wider range of clock frequencies and control signals from | signals.

I FIG. 1 shows a structured | heme of the proposed converter; Hja FIG. 2 are timing diagrams showing the operation of the converter.

The converter contains the 1 set-up bus, the 2-start bus, the 3-pulse puller, the H-HE4 element triggers 5 and 6, the II-II element 7, the count of 8 pulses, the output bus 9 and

w | 10 input code.

; The Converter operates as follows. .

; Before the start of operation on bus 1 of the initial installation, an impulse (| 4) ig.2a) is applied, through which the generator 3 and pulses are set to the initial state, triggers 5 and 6 and the counter 8, on the information inputs of which the time code is set. HJoro interval. When applying a pulse n | a tshgnu 2 run (Fig. 26), on his

The converter is a code-time interval containing the first and second triggers, the first inputs of which are combined and connected to the output of the pulse meter, whose information inputs are the corresponding buses of the input code, and the pulse generator, the output of which is connected to the second INPUT of the second trigger, whose output is output shi ni, characterized in that, in order to improve performance and expand the area of application by providing the ability to work in a wider range of clocks

the leading edge is triggered by a generator (er 3 pulses (Fig. 2c), which begins its work from the leading edge of a clock pulse. The first clock frequency and control signals, the howl pulse passes on trigger 6, the first and second elements are entered n | front front install it

AND-NOT, the first inputs of which are combined and connected to the output of the pulse generator, the first input of which is the start bus, and the second input is connected to the output from a 1ftch pulse, the recording input of which is combined with the second input of the first trigger and connected to the first input 45 NAND, and the subtracting input is connected to the output of the second NAND element, the second input of which is connected to the output of the second trigger, the third input of which is combined with the third input of the first trigger, the reset input of the pulse counter and the third input of the pulse generator This is the bus of the initial installation, while the second input of the first AND-NAND element is connected to the output of the first trigger.

in 1 (fig.2k), passes through the open element AND-NOT 4 (fig.2g) to the input of the preliminary recording of information of the estimator 8, the leading edge carried out | writing code into it (FIGS. 2e and 2g), passes through the opening element AND-NOT 7 to the input of counter 8, the falling edge of the first clock pulse triggers trigger 3 (FIG. 2d), the potential at the output of which blocks AND-NOT 4 in order to prevent the passage of interference to the pre-entry of the counter 8. On the falling edge of the clock pulses fed to the subtracting input of the counter 8, a countdown is made (Fig. 2c, 2e and 2g). Simultaneously with a clock pulse,

transferring the triggers of the counter 8 from O to 1, the output of the counter 8 pulls a pulse, on the leading edge of which a trigger 6 is set to the initial state (FIG. 2c and 2k), thereby processing the specified time interval, and also stopping the operation and resetting the pulse generator 3. Trigger 5 is triggered on the falling edge of this pulse, removing the prohibition from the second input of the NAND 4 element, with the result that the converter returns to its original state before the next trigger pulse arrives via the start bus 2.

Claims (1)

Invention Formula The converter is a code-time interval containing the first and second triggers, the first inputs of which are combined and connected to the output of the pulse meter, whose information inputs are the corresponding buses of the input code, and the pulse generator, the output of which is connected to the second INPUT of the second trigger, whose output is output shi ni, characterized in that, in order to improve performance: and to expand the area of application by providing the ability to work in a wider range of clocks frequencies and control signals, the first and second elements are entered into it frequencies and control signals, the first and second elements are entered into it AND-NOT, the first inputs of which are combined and connected to the output of the pulse generator, the first input of which is the start bus, and the second input is connected to the output from a 1ftch pulse, the recording input of which is combined with the second input of the first trigger and connected to the first input NAND, and the subtractive input is connected to the output of the second element NAND, the second input of which is connected to the output of the second trigger, the third input of which is combined with the third input of the first trigger, the reset input of the pulse counter and the third input of the generator pulse and a bus is the initial setup, the second input of the first AND-NO element is connected to the output of the first flip-flop. auQ S 8 y d P LPS L ng FIG. 2