SU1257825A1 - Minimum duration pulse discriminator - Google Patents

Abstract

The invention can be used in automation devices for extracting pulse signals whose duration is less than a predetermined limit. The purpose of the invention is to expand the functionality of the selector. The device contains a trigger 7, the element And 2 and the driver 10 strobing, their pulses. Introduction of the reference pulse generator 1, the AND 3 element, the 4 pulse counter, decoder 5 and 6, the prohibition element 8, the OR 9 element and the trigger 11 enables the device to restore the original duration of the selectable pulses by writing off the information accumulated in the 4 pulse counter time of action of the input pulse immediately after its termination. 2 Il. ND SL 00 N: SL

Description

The invention relates to a pulse technique and can be used in automation devices for extracting pulse signals whose duration is less than a predetermined limit.

The aim of the invention is to extend the functionality by allowing the output device to restore the initial duration of the selected pulses by writing off the information accumulated in the pulse counter during the input pulse immediately after its completion.

Figure 1 shows the functional diagram of the device; figure 2 - timing diagrams, as shown, his work.

The device contains a reference pulse generator 1, elements 2 and 3, pulse counter 4, decoders 5 and 6, trigger 7, prohibition element 8, element 9 OR, gate driver 10, trigger 11, input 12 and output 13 of the bus.

The output of the reference pulse generator 1 is connected to the first inputs of the first and second elements 2 and 3 And, the outputs of which are connected respectively with subtracted and summed, with the inputs of the pulse counter 4, the corresponding outputs of which are connected to the inputs of the decoders 5 and 6, the output of the first of which connected to the installation input of the zero trigger 7, the installation input of the unit of which is connected to the output of the prohibition element 8 and the first input of the element 9 OR. The direct input of the inhibit element 8 is connected to the output of the gate clock pulse generator 10, the input of which is connected to the inverse input of the inhibit element 8, information and clock inputs of the trigger 11 and the input bus 12. The output of the trigger 11 is connected to the second input of the element 2 And, and the input of the zero setting - with the output of the element 9 OR, the second input of which is connected to the reset input of the pulse counter 4 and the output of the decoder 6. The output of the trigger 7 is connected to the second input of the element 3 AND and the output bus 13.

The pulse selector of the minimum duration works as follows.

In the initial state, the pulse counter 4, representing the n-bit reversible counter, triggers 7 and 11 are in the zero state. When a pulse having a duration tn less than the specified time threshold tnop arrives at the input bus 12, the trigger 11 is switched and the gate generator 10 is started, the pulse duration of which determines the time threshold tnob.- G, where n is the number of bits of the pulse counter 4; f is the pulse repetition frequency of the reference pulse generator 1.

The trigger 11 is set to one state, and through the first element 2 and the pulses from the reference pulse generator 1 are fed to the summing input of the counter

five

pulses 4. The prohibition element 8 is triggered on the falling edge of the input signal, the inverse and direct inputs of which receive the input pulse and the pulse from the gate generator 10. The output signal of the prohibition element 8 through the element 9 OR is fed to the R input of the trigger 1 and sets it to the zero state, thereby stopping the arrival of the reference pulses.

through the element 2 and the pulse counter 4. The signal from the output of the prohibition element 8 simultaneously sets the trigger 7 to the one state via the S-input, with the result that pulses from the generator of reference pulses start to flow to the subtracting input of the pulse counter 4 through the element 2 And. At the point in time when the pulse counter 4 is in the zero state, the output of the first decoder 5, which is the zero state decoder

0 of the pulse counter 4, a signal appears which sets the trigger 7 to the zero state on the R input, as a result of which the pulses from the reference pulse generator 1 through element 3 stop at the pulse counter 4. From the direct

5, the output of the trigger 7 on the output bus 13 receives a pulse with a duration equal to the duration of the input pulse. The device is ready to receive and analyze the next input pulse. If the duration of the input pulse is greater than the time threshold tn iaop0, then the trigger 11 is set to one and allows the arrival of pulses from the reference pulse generator 1 through element 2 And to the summing input of the pulse counter 4. The prohibition element 8 in this case does not work, and the trigger 7 remains in the zero state. At the moment when the pulse counter 4 is in the single state, the output of the second decoder 6 is a pulse arriving at the reset input of the pulse counter 4 and through the element 9 OR at the R input of the trigger 11, the pulse counter 4 and trigger 11 is set to the zero state. When the pulse counter 4 is set to the zero state, a pulse is generated at the output of the first decoder 5, which is fed to

5 The R input of trigger 7 confirms its zero state and the absence of a signal on the output bus 13. If the duration of the input pulse is equal to the time threshold, prohibit element 8 will not work, and trigger 7 will be in the zero state. AT

0 time, when the pulse counter 4 will be in the unit state, the first and second decoder 5 and b will work, resulting in the pulse counter 4 and the trigger 11 are set to the zero state and the zero state of the trigger 7 is confirmed and no signal is output bus 13. Thus, the proposed device provides a selection of input pulses.

the duration of which is less than a predetermined limit, this ensures the formation of output signals whose duration is equal to the duration of the input pulses.

invention formula

A pulse selector with a minimum duration, containing an input and output bus, a gating pulse driver, a first AND element and a first flip-flop, the output of which is connected to the first input of the first AND element, characterized in that, in order to extend the functionality devices of the initial duration of the selected pulses, a prohibition element, a second trigger, a pulse counter, the first and second decoders, the OR element, the second And element, and the generator PORN pulses, whose output is connected to a second

the input of the first and the first input of the second elements And, the outputs of which are connected respectively to the subtractive and summing inputs of the pulse counter, the corresponding outputs of which are connected to the inputs of the first and second decipherors, the output of the first of which is connected to the input of the zero setting of the first trigger, the output of which is connected to the output bus , and the unit setup input — with the first input of the OR element and the output of the prohibition element, the direct input of which is connected to the output of the gating driver, the input of which is connected to and the inverse input of the prohibition element, the input bus and the information and clock inputs of the second trigger, the output of which is connected to the second input of the second element AND, and the input of the zero setting are connected to the output of the OR element, the second input of which is connected to the output of the pulse counter.

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Claims (1)

Claim A pulse selector of minimum duration, containing an input and output bus, a gate pulse shaper, a first element And a first trigger, the output of which is connected to the first input of the first element And, characterized in that, in order to expand the functionality by providing the possibility of restoring the original device output duration of the selectable pulses, a prohibition element, a second trigger, a pulse counter, the first and second decoders, an OR element, a second And element and a support generator are introduced into it s pulse, the output of which is connected to a second 20 input of the first and the first input of the second AND gates, whose outputs are respectively connected to the pulse counter subtraction and summing inputs respectively ₅ stvuyugtsie outputs are connected to inputs of the first and second decoders output the first of which is connected to the input zeroing of the first trigger, the output of which is connected to the output bus, and the input of the unit is connected to the first input of the ¹⁰ OR element and the output of the inhibit element, the direct input of which is connected to the output of the driver gating pulses, the input of which is connected to the inverse input of the inhibit element, the input bus and the information and clock inputs of the second trigger, the output of which is connected to the second input of the second AND element, and the zero-setting input is connected to the output of the OR element, the second input of which is connected to the output of the second decoder and a pulse counter reset input. / IIIIIIIIIIIIIIIIIIIIIII II 1 I 1 1 II LI L1J________ input 12 _____ - t _U £ .trropX ------------ 1 tu-xt pore I ------------- -11 ___________ I ------------------- 1 ________________________ I ---------------------------- -----------------------1_______________________ 10 ________ I ----------------------- 1 _____________ I ------------------------ 1 ------------------------------------- 8 __________ I — I --------- --------------------- 713______________________I I _______________________, __________________________________ fi8.2