SU748803A1 - Digital filter - Google Patents

Description

(54) DIGITAL FILTER

one

The invention relates to radio engineering and can be used in devices for digital filtering narrowband signals in the background of noise and interference; five

A digital filter is known comprising an inverter, a counting direction change block, a reversible counter, a match element, and a trigger 1.

However, the filter has a drawback, | Q i. it does not respond to different amplitudes of the input signals, and, moreover, even a brief disturbance causes device malfunctions.

Also known is a digital filter containing a counter, elements, matches, controlled by a software device, triggers, OR and AND elements, a delay line, and a controlled cry 2.

The nature of the input signal is accepted by the device without taking into account the current value of its amplitude and therefore the device, having even a small amplitude, can be skipped with the output key 25. In addition, short-term interference leads to improper operation of the device.

The purpose of the invention is to improve the filtering of the signal at different values

noise level and increase the reliability of the device.

The goal is achieved in that a digital filter containing a counter, the outputs of which are connected to the inputs of two AND elements, the outputs of which are connected to the inputs of a trigger connected by the output to the first input of the third element AND, and the OR element, is inserted into an analog-to-digital converter, pulse shaper , code entry gates, additional triggers {additional genes, additional counters ---, an additional element | OR and additional elements AND, while the outputs of the analog-digital converter are connected to the first inputs of the gates code records and to the inputs of the additional element OR, whose output is through a pulse shaper with the R input of the first additional trigger, with the first input of the OR element and with the second input of the third element AND, whose EXIT is connected to the R input of the additional trigger, the second inputs of the recording gates the codeconnected to the output of the first additional element I, whose inputs are connected to the outputs of the counter, the counting input of which 748803 is connected to the inverse output of the first additional trigger, 3- and C-inputs of which are connected to the output the OR element, the second input of which is connected to the output of the second element AND, the outputs of the code entry gates are connected to the bit inputs of the first additional counter, the output of the cotbrogs is connected to the J and C inputs of the second additional trigger, the inverted output of which is connected to the first input of the second additional And, the second input of which is connected to the bus clock pulse, and the output with the counting inputs of additional counters, the second input of which is connected to the bus: reset pulses, a. outputs - to the inputs of the third additional element I. The drawing shows the function on the digital filter circuit. The digital filter contains an analog-to-digital converter (ADC) 1, element 2 OR, a driver of 3 pulses on the front and decay with interference suppression, element 4 OR, trigger 5, counter 6, elements 7, 8 and 9 AND, gates 10 code entries (elements AND ), counter 11, element 12 I, trigger 13, counter 14, trigger 15, elements 16 and 17 I. The output signal goes to bus 18, clock pulses to bus 19, reset pulses to bus 20. Output signal is removed from bus 21 In the initial state, the counters 6, 11, and 14 and trigger 15 are set to zero, and the three heres 5 and 13 are set to one (for the national schema corresponding links are not shown). On bus 18, the zero signal, at the outputs of the analog-digital converter 1, zero signals (the functional diagram shows, for example, a four-bit ADC), and at the outputs of all elements, And, zero signals. The digital filter works as follows. After the input signal exceeds the quantization level of the A / D converter 1, the output signal of element 2 OR is established on the bus 18 OR until a signal is present on at least one of the outputs of the A / D converter 1. On the front of the signal at the output of element 2 OR shaper 3, a front pulse is inserted that sets trigger 5 to zero, allowing counter 6 to work. Counter b is combined with elements 8 and 9 of the signal to control the half-time of the input signal. The pulses from the outputs of these elements And initiate and discharge from; the trigger 15, forming a gating pulse. If the decay pulse of the imaging unit 3 is detected at the moment when there is a gating pulse at the output of the trigger 15, this means that the full-wave oscillation has a predetermined frequency within the limits determined by the gating pulse duration. The end of the pulse at the output of element 2 OR through element 4 OR trigger 5 returns to the initial unit. At the end of the strobe pulse, the pulse from the output of element 2 OR the cutter element 4 OR also returns the trigger 5 to the initial single state. The zero potential from the inverse output of the trigger 5 prohibits the operation of the counter 6 and sets it to the zero state. Element 7 And together with counter 6 serves to estimate the amplitude of the incoming oscillation and further, if this oscillation is considered to be a useful signal according to the selected criteria, record 14 in the hot counter 14 proportional to the amplitude of the input signal. The ego is produced as follows. At the output of element 7 and at the time corresponding to the middle of the first half-period of oscillation (maximum amplitudes, expected sinusoidal oscillations), code entry gates 10 are written into the additional code counter 11 relative to the code issued by the ADC 1. The pulse at the output of element 16 sets the trigger 13 to the zero state, allowing the operation of element 12 I. After counter overflow 11, trigger 13 prohibits the passage of clock pulses through element 12 I. The number of pulses at the output corresponds to the number issued earlier with ADC 1, and these pulses go to counter 14 ... During the subsequent half-periods, input-. In the same way, a number is written in the counter 11, which characterizes the amplitude of the input signal, and, in the case it turns out to be useful (the signal frequency corresponds to the given one), further information is accumulated on the input signal in counter 14. Element 17 And serves to output the output pulse in case of reaching a certain (threshold) number accumulated in the counter 14. Moreover, this number should be accumulated over a certain period of time determined by the period of the reset pulses on ine 20. In order to work as close as possible of the device to the analog filter, it is necessary to produce only a partial zeroing of the counter 14 to reset pulses. The digital filter estimates the amplitude of the input signal and the multiple accumulation of the results of this evaluation, which makes it possible to correctly estimate the energy of the useful signal and interference and improves the filtering of the useful signal at different levels of interference.

With the continuous accumulation of information about the input signal having a given frequency, in the counter 14 and with partial zeroing of the counter 14, the information accumulated in the counter is averaged at predetermined time intervals, which allows the device to not respond even to several periods of interference.

To increase the reliability of the proposed device, as a driver 3, a pulse shaper along the front and fall is used, not output for short-term single and zero interferences, the output pulses of the front and fall on their outputs. In this case, short-term single and zero noise in shaper 3 may trigger preliminary triggers and, after controlling the duration of the input signal, it is decided to issue or not output pulses to the outputs.

Thus, the shaper 3 with some delay produces output pulses, and all the pulses,. the duration of which is less than this delay is considered interference and the driver 3 does not output output pulses to nn.

The use of such a driver in the device Hq occurs a false start, as well as resetting the trigger 5, allowing the operation of the counter 6.

In addition, if the driver 3 did not have noise immunity from short-term interference, a false downward impulse from one of the outputs could, under certain conditions (in the presence of a gate at the output of the trigger 15), produce a false accumulation in the counter 14. Thus, interference from the device from short-term interference, disrupting its proper functioning, and increased reliability of its operation.

In addition, the return of the trigger in 5 and 13 to the initial single state is made by ito decay of the pulse entering the i- and C-inputs, and the low potential is fed to the K-input. This design of the device circuit is reliable, since Switching

1 triggers occur after issuing img

the pulse at the output of element 9 I, or after switching to the zero state of the most significant bit of the counter 11. In the case of using RS-flip-flops, at the moment of switching of the flip-flops 5 and 13 into the single state, it went off. be the acceleration of the output pulse and then it would be necessary to consider a number of moments associated with the transient

processes that disrupt the correct functioning of the device as a whole. Therefore, the use as triggers 5 and 13 RS-triggers is undesirable.

Claims (2)

1. Author's certificate of the USSR 512559, cl. H 03 H 7/10, 1974. 2. USSR author's certificate  365799, cl. H 03 H 7/02, 1971 (pro-otip). / ..