SU1243115A1 - Multichannel generator of single pulses - Google Patents

Abstract

The invention can be used in automation, computing, control and test systems. The purpose of the invention is to increase the speed and expand the functional capabilities of the device. The shaper contains a generator of 4 stable frequency pulses, a frequency divider 8, synchronizers 12 and 13, a shaper of 14 pulses and a D-flip-flop 21. Introduction to the buffer registers 1 of the program code, registers 3 of the code-program, paraphase command capture block 5 7 frequency phasing, synchronization unit 9 consisting of N channel synchronizers 10. 1-10.N and 11.1-11.N, readiness shaping unit 16, cycle duration shaping unit 18, LI element 22, AND 23 element and D-flip-flop 24 formation of the back front provides pro rammiruemoe temporal change pulse parameters, generated in each channel. 9 il .. from C /) to li oo ate

Description

one

The invention relates to a pulse engineering technique and can be used in automation 5 of computing technology, test control systems.

The purpose of the invention is to increase the speed and spread of the functionality by providing a programmable change in the temporal parameters of the generated pulses in each channel,

Fig. 1 shows a structural scheme of a multichannel single pulse generator, in Figs. 2-6, respectively, structural diagrams of a paraphase block for capturing a command of a frequency phasing block, a channel synchronizer, a channel formating pulse generator, and a FORMATION forming unit in FIG. 7–9 are diagrams of stresses that show the work of the shaper,.

The shaper contains buffer registers 1 of program code, the inputs of which are connected to information buses 2, registers 3 of program code, generator 4 stable frequency pulses, paraphase command capture unit 5, whose input is connected to control input bus 6, frequency phasing unit 7, divider 8 frequency, synchronization unit 9, consisting of M channel synchronizers 10.1-1: 0, h / and M channel synchronizers 11.1-11, k |, synchronizers 12 and 13, shaper 14 pulses, sos; from H channel shapers 15,1-15, j pulses, block 16 is formed readiness, the output of which is connected to the output bus 17 of the control, block 18 of forming the duration, cycle, M output channel formers 19.1-19, M, the outputs of which are connected to the channel buses 20.1-20fW, Each output channel former 19 consists from the output trigger 21 (type D), the element IL 22, the element I 23, the trigger 24 forming the back of its front (type D).

Paraphase block 5 (Fig, 2) capture command contains the element And 25, the elements of OR 26-28, triggers 29 and 30 of the capture.

Block 7 (fig. 3) of the phasing-frequency contains a phase trigger 31, elements I. 32 and 33, element OR 34, iversion 35 and 36,

Channel synchronizer (figure 4) contains the inverter 37, the elements And 38

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25 -, jg

55

35

40

45

152

and 39J, an element OR 40, and the composition of all channel synchronizers 10.1- .10. MS ri, 1-1t.M ,, as well as sync. Topoi 12 and 13 are identical.

The rock impulse driver (Fig. 5) contains comparison nodes 41 and 42: the composition of all channel formers 15.1-15. the pulses are the same.

The readiness shaping unit 16 (FIG. 6) contains a comparison node 43, a trigger 44 (type D), and is identical in composition to a cycle duration shaping unit 1j8,

 The shaper operates as follows.

Let us first consider preparing it for work and interacting with an external device that is not part of the invention and controls the work. shaper, which is characterized by two main phases,

In the first phase, a working cycle occurs: the process of forming a single: mpule; cpv on tires 20.1-20. N. Entry Into the duty cycle is carried out according to a command received on bus 6. Worker 1} rkpu corresponds to a low potential level at the output of block 18.

 In the second phase, waiting is the initial state to which the driver arrives after the end of the working cycle and in which it is before the arrival of the next command. The expectation corresponds to a low potential level (logical O) at the outputs of tr: nggers 29 and 30, as well as at the direct outputs of the flip-flops 21 of all output channel drivers (19.1-19.10), while the outputs of the flip-flops 44 blocks 16 and 18 and respectively on the tire. 17 there is a high level potential (logic 1), Logical 1 from the output of the trigger 44 of the block 18 is fed to the installation input of the frequency divider 8 and brings it to the corresponding state. In addition to TorOj, logical 1 acts on the inverter input, 36, from the output of which logical 0 hits the first inputs of elements I 32 and 33, blocks the passage through them of imp: pulsed sequences arriving 1 x on the second inputs of these elements And from the direct and inverse outputs of the generator 4, respectively. Thus, the pulse sequence

i.e. clock frequency, there is no frequency at the counting input of the divider 8 and at the clock inputs of the synchronization unit 9 — the first inputs of the And 38 elements and the first inputs of the And 39 elements, as well as at the first inputs of the elements 26 and 27 of the block 5.

Logical 1 from the output of the trigger 44 also arrives at the first input of the element AND 25 to creates conditions for the command to pass through it when it arrives at the second input of the element 25 from the bus 6. The presence of a command corresponds to a high level potential. During the working cycle, registers 3 store the program code, which, for the duration of the working cycle, sets the values of the variable parameters of the generator, which determine:

1. The combination of those channels from the total number N, which should form a single pulse in a given working cycle. This parameter is set by the code at the outputs of registers 3, which program the selection of channels.

2. The fronts (front or rear) of the clock frequency pulses, which determine the switching times of the output flip-flops 21, which generate pulses at the output of each of the channels. This parameter is set by the code at the outputs of registers 3, which program the phase of the synchronization frequency.

3. Position of the leading edges of the pulses at the output of each channel relative to the beginning of the working cycle and within this working cycle. This parameter is specified by the code.

at the outputs of registers 3, programming the position of the leading fronts.

4 „The position of the rising edges of the pulses at the output of each of the channels relates to the beginning of the working cycle. This parameter is specified by the code at the outputs of registers 3, which program the position of the falling edges. Moreover, the programming of the trailing edge position allows for the formation of pulses of 5 duration — which covers several work cycles;

5, The time of occurrence of the Ready signal (logical 1) on bus 1 relative to the start of the work cycle. The Ready signal enables the external device to issue a next command and informs it of the end

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processes that are initiated by pulses from the driver outputs. This parameter is set by the code at the outputs of the programmers when they are ready. Loss of signal This efficiency (log ical O) indicates that the command is received by the driver.

6. The duration of the working cycle, the end of which indicates the readiness of the driver to receive the next command. This parameter is set by the output of registers 3 programming the duration of the cycle.

Timing diagrams of signals that provide interaction between the imaging device and an external device in asynchronous mode are shown in Fig. 5 (a, b, b, d).

The time intervals during which the shaper may be prepared for the next duty cycle are shown in Fig. 5o. Preparation consists in a complete or partial change of the program code in registers 1. The initiator and performer of such a change is an external device. Consider now the work of the driver as a whole. At an arbitrary point in time, relative to the frequency period of the generator 4, the bus 6 and then the second input of the AND 25 element receives a command (logical 1). In this case, the logical 1 from the output of the element And 25 comes to the recording input 3 and overwrites the program code from the registers 1 to the registers 3, in addition, the logical 1 enters the information inputs. flip-flops 29 and 30 of block 5; Synchronous inputs of these flip-flops from the direct and inverse outputs of the generator A receive pulse sequences in the form of two meanders that are phase-shifted 180 relative to each other, assume that the coincidence in time of logical 1 at the information input and the leading edge of the pulse at the sync input will occur earlier in trigger 29, which will cause it to switch and logical .1 from its output through the OR element 27 will go to the setup input of trigger 30 and prevent it from switching. In addition, logical 1 arrives at the first input of trigger 31 and sets logical 1 to its direct output. In the event that conditions were previously created for switching at inputs of trigger 30, then logical 1 from its output disables switching of trigger 29 and sets logical 1 at the inverse output of the trigger 31. Thus, the command is captured and the phase of the frequency is memorized at the moment of capture. Logic 1 from the output of one of the triggers, heres 29 and 30 through the OR 28 element is sent to the setup input of the trigger 44 of block 16 and the similar trigger of block 18 and a call There is no change in the level of the signals at their outputs, which corresponds to the removal of the Ready signal from the bus 17 and the beginning of the working cycle of the drivers. With the appearance of a logical O at the output of block 18, a reset signal is removed from the frequency divider 8, the command input of block 5 is blocked by logical O at the first input of the element. AND 25 and the enabling potential (logical 1) is set at the first inputs of elements 32 and 33, one of Depending on the state of the trigger 31, connected with the second inputs of the elements 32 and 33, they transmit to their output a pulse sequence transmitted to its third input from the corresponding output of the generator 4. ohm and inverse outputs of block 7, which synchronize the operation of other blocks of the imaging unit. The first pulse from the direct output of block 7 through the elements OR 26 and 27 goes to the setup inputs of the flip-flops 29 and 30 and returns one of them to the initial state (logical O output). The operation of blocks 5 and 7 is illustrated by the time diagrams of FIG. 6 ,. .

The clock pulses from the direct output of block 7 and the pulse sequence are shifted relative to it in phase by 180 (the clock frequency is shifted), from the inverse output of block 7 are received respectively by. the first and second clock inputs of block 9 and further to the corresponding first inputs of elements 38 and 39 of synchronizers 10.1-10.W, 11.4-11, M, 12 and 13. To the second inputs of elements 38 and through inverters 37 to the second inputs of elements 38, and through the inverters 37 to the second inputs of the elements 39 enters programming information with the corresponding 5 0 0 5

five

five

0

depending on the specific program code of the clock frequency on the outputs of the AND 38 elements or the shifted clock frequency on the output of the AND 39 elements. Thus, a set of certain -pulse sequences is formed; which from the outputs of the synchronizers 10.1 -10. M bitwise distributed along the clock inputs of the flip-flops of the 21 respective channels. The positions of the leading edges of the pulses of these sequences determine the possible moments of switching of these triggers during the formation of the leading edges of the pulses at the outputs of the channels.

A similar task is performed by synchronizers 11.1–11, whose outputs, affecting the two-way inputs of the flip-flops 21 of each channel, determine the possible positions of the falling edges of the pulses at the outputs of the channels. The outputs of the synchronizers 12 and 13 op. The possible moments of the occurrence of the Ready signal (bus 17) and the end of the work cycle are determined.

After the first pulse of the clock frequency (FIG. 7) coming from the direct input of block 7 to the counting input of the frequency divider 8, it transitions from the initial zero state to the first, whose code from the counter outputs goes to the first inputs of nodes 41 and 42 comparison of all channel drivers 15,1-15, W pulses and is compared with the codes received at the second inputs of comparison nodes 41 and 42 from corresponding outputs of registers 3. For comparison node 41, these are outputs that program the leading edge positions, and for comparison node 42 - outputs programming e frontov..Polozhitelny rear position comparison result as a logical 1, in this teaching in eating from node 4 outputs | comparison (15.N), is fed to the second input of the element And 23 of the first channel {. at the first input of the cat there is a logical 1 corresponding) code bit c. In the code of registers 3j of programming, the selection of channels ,, Logic 1 from the output of the element AND 23 through the element OR 22 enters the information input of the trigger 21, the nearest pulse from the output of the synchronizer 10. K1 switches the trigger 21 with its leading edge and

71

thereby forming the leading edge of the pulse at the output of the first channel 20, N. Logical 1 from the output of trigger 21 is fed to the second input of the element OR 22 and supports logic 1 at the information input of the trigger 21 after the logical 1 disappears at the first input of the element OR 22 when the frequency divider changes its state.

Upon execution of the frequency divider of the second division cycle, coincidence was detected by the node 42 comparing the channel pulse driver 15.W and logical 1 will go to the information input of the first channel trigger 24. The nearest pulse from the synchronizer 11.1 output will go to the sync input of the first channel trigger 24 and its front front will cause it to switch. Logic 1 with the outputs and the trigger 24 affects the installation input of the trigger 21, returns it to its original state. This forms the leading edge of the pulse at the output of the first channel. Logical 1 from the inverse output of the trigger 21 is fed to the setup input of the trigger 24 and it also switches to the initial state.

When the frequency divider performs four cycles, the code at its output will coincide with the code at the outputs of registers 3 which specify the moment of issue of readiness, which is fixed by comparison unit 43 of block 16. Logical 1 from its output will go to information input of trigger 44, which will switch on the leading edge of the pulse from the output of the synchronizer 12 and on the Shing 17, the high potential potential is on. The signal of the splitter 8 of the frequency nocj; e of the five division cycles is recorded simultaneously by both nodes 41 and 42 comparing the channel driver 15. N pulses and a pulse is formed on the 20 M bus similarly to that obtained at the output of the first channel, and its duration is equal to 1 / 2T clock frequency. In addition, the output code of the frequency divider 8, after five cycles, coincides with the code at the output of registers 3, which defines the duration of the cycle, and block 18, similar to block 16, gives a logical 1, which will complete the transition

5 o

five

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five

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0

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l from duty cycle to standby state

yes neither.

Claims (1)

Invention Formula A multichannel single pulse shaper containing W formation channels, a stable frequency pulse generator, a pulse shaper, the inputs of which are randomly connected to the outputs of a frequency divider, an output trigger in each channel, in order to increase speed and expand functional capabilities due to the provision of a programmable change in the temporal parameters of the generated pulses in each channel, the paraphase command pickup unit, the phasing unit are additionally introduced into it frequency, readiness shaping unit, cycle duration shaping unit, synchronization block, program code registers, program code buffer registers, and a falling edge trigger, an AND element and a RSHI element are entered into each of the N formation channels, the command input of the paraphase unit, command capture is connected to the input control bus, and its first and second clock inputs are connected respectively to the direct and inverse outputs of the stable frequency generator, as well as to the first and second clock inputs of the phasing unit and frequencies, which by their first and second phasing inputs are connected respectively to the first and second phasing outputs of the paraphase command capture unit, recording the output of which is connected to the recording inputs of the program code registers, and the trigger output is connected to the starting inputs of the readiness shaping unit and the cycle duration shaping unit, the output of which is connected to the installation input of the frequency divider, as well as to the enabling input of the paraphase command pickup unit and the blocking input of the phasor unit frequencies, the direct clock output of which is connected to the setup input of the paraphase command capture unit, to the counting input of the frequency divider and to the first clock input of the synchronization unit, the second clock input of which is connected to the inverse clock output of the frequency phasing unit, information inputs of the program 9 code buffer registers. 1 we are connected to informational n (inam, and their informational codes to informational inputs of program code registers, whose first outputs, which program the selection of channels, are connected to the first inputs of the AND elements of each channel, and the outputs that program the phase of the synchronization frequency, bitwise are connected to the programmable inputs of the synchronization unit, the first outputs of which are bitwise connected to the sync signals of the output triggers of each channel, the direct outputs of which are connected to the corresponding channel buses and to the first inputs of the corresponding RSHI elements, the outputs of which are connected to the information inputs of the corresponding output triggers, the second outputs of the synchronization unit are connected in parallel to the synchronous inputs of the trigger edges of the formation of each edge of the channels, the outputs of which are connected to the installation inputs of the corresponding output triggers, the inverse outputs of which are connected to to the installation inputs of the corresponding trigger formation of the trailing edge, the outputs of the program code registers, the programming positions of the front x fronts, and outputs programming polo11510 Zhenie;) the front edges of the output channel attributes are connected respectively to the bit one and the first and second inputs of the pulse former, the outputs of which determine the positions of the leading edges are bitwise connected to the second inputs of the elements And of each of the channels whose outputs are connected to the second inputs of the corresponding OR elements, and the pulse driver outputs, which determine the positions of the falling edges, are bitwise connected to the information inputs of the trailing edge trigger triggers, the outputs of the program code registers, limit the availability of the ready signal, are connected bitwise to the programmable inputs of the readiness block, the output of which is connected to the output control bus, and its current inputs are connected in parallel to the outputs of the frequency divider and to the inputs of the current conditioner of the cycle duration programmable the inputs of which are connected in series to the outputs of the nporpajviMbi code registers, the synchronization inputs of the readiness shaping unit and the duration shaping unit are connected to the corresponding j interface; Am sync block. SM.i M & F .S Js W TO) ff TO .y K23 FIG. 6 FIG. 7 ./ / t Fig.c Editor L.Gratillo Compiled by, Geras: im Techred N. Bonkalo Order 3717/56 Circulation 816 Subscription VNIIPI State, on the USSR Committee  on affairs of inventions and open-ing 113035, Moscow, Zh-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, st. Design, And FIG. 9 Proofreader S. Shekmar