SU960812A1 - Controllable random number generator - Google Patents

Description

(54) CONTROLLED GENERATOR OF RANDOM NUMBERS

The invention relates to computing and can be used in statistical modeling in digital computers.

The P-ZESTEN controlled random number generator contains a sensor of uniformly distributed random numbers, a memory device of a parallel comparison circuit, triggers, coincidence circuits, an output device and allowing to obtain random numbers with a given distribution law for one sensor cycle. | l.

However, the device has a high complexity.

A generator is also known that contains a generator of uniformly distributed random numbers, a comparison circuit, a memory, a logarithmic block, a clock pulse generator 2j.

The disadvantage of the device is its low speed, since the t-bit ct is a unique number. Ruetz vm + 1) time.

The closest technical solution to the invention is a random number generator, a holding clock generator, a generator of uniformly distributed random numbers, the input of which is connected to the first output of the clock generator, a memory device, the comparison circuit, the first and second groups of inputs of which are connected to the outputs of the memory devices and a generator of uniformly distributed random numbers, respectively, the first and second groups of elements AND, the decoder, the registration table, whose outputs are decoder connected with the first group

15 memory inputs, the second memory input is connected to the nepEioMy output of the clock generator, the register inputs are connected to the outputs of the first group of elements And; the first and second groups of inputs of which are connected to the outputs of the comparison circuit and the clock pulse generator, respectively, the register outputs through the second

25, the group of elements I is connected to the output of the device, the output of the generator of clock pulses is connected to the second group of inputs of the second group of elements I. In the generator to obtain

30 sequences of random numbers

with a given distribution law, a functional transformation is applied based on a piecewise linear approximation of a given distribution F (x) GZ.

However, the known generator has a low accuracy, since the range of possible values of the argument x is divided into n equal intervals,

The aim of the invention is to improve the accuracy of the distribution of F (x) by dividing the range of values of the argument x into l unequal intervals.

The goal is achieved by the fact that a controlled random number generator, containing a clock: pulse generator, memory unit, first decoder, first memory register, the output of which is connected to the first input of the memory unit through the first decoder, comparison unit, first and second blocks And elements, the generator of uniformly distributed numbers, the group of outputs of which is connected to the corresponding inputs of the first group of 6JiOKa comparison, the output of the second block of elements And is the generator | Tora output, the second and third memory registers are entered , code analysis block, counter, second decoder and OR element, the first and second Start inputs, as well as the second to the second inputs of the clock generator connected to the first and second 1 inputs of the generator f (n is the number of outputs of the second decoder) the output of the second decoder and the first output of the block of code analysis, respectively, lane: e -., the first output of the clock generator is connected to the first input of the counter, to the first input of the second And elements, the second and third inputs of which are connected to the output of its third register ;, memory and access 1eners: bargaining. uniformly distributed random numbers, respectively, the second output of the clock pulse generator is connected by the first inputs of nepsoio and the second memory registers, the memory block and the code analysis unit, the first output of the block is connected to the second input of the second register rtaMHTH, whose outputs are connected (corresponding to DI1Mi and inputs the second group of the comparator unit, the input of which is connected to the third output of the clock pulse pulse, the second output of the memory block connect:.: tea to the second input of the first memory register, the third input of which is connected to the second output of the 5noia code analysis, the second and third inputs of which are connected to the network output of the memory unit and the output of the cp unit; output, respectively, the fourth t-cell generator;

clock to .- :: 1ulso is connected to the input generator of randomly divided random numbers and numbers, the output group is connected to the corresponding first group of the first block of elements And, the second group of which is connected to the corresponding outputs of the second decoder, Г and output4 of the first the block of elements AND is connected to the group of inputs of the element OR, respectively, the input of which is connected to the output of the comparison unit, and the output of the element OR is connected to the perglom input of the third memory register, whose second input is in conjunction with The second output of the clock generator, the sixth and seventh BOXES of which are connected to the second input of the counter and the input of the second de: lifter, respectively, the fourth input of the first memory register is connected to the nth output of the VTO1 decoder, the INPUT group of which is connected to the inputs, respectively.

In addition, the code analysis block contains four groups of AND elements, the OR element, the NOT element, and two memory registers, whose peaks form the first input of the block, the second input of which is co-inserted with the second: - or the inputs of the memory registers, com. connect with the first INPUT 3.j3iv SHTa OR, exit e:; ements And the second group LE. i the first output 6JiOfca, zykhod: the elements of the third and the couple are his and his g:; sadi; eny, respectively, with - “tod IdM and the third inputs of the E.1I element, whose output is BTOpHjx-i bchoka output, the first output The first reggaeter of memory is connected to the first inputs of the first and third groups;., BJ: The first output of the first memory register is connected to the first inputs of the elements of the second and fourth groups, the first output of the second memory register is 1 g connected to each other. oo- Both the first and second groups, the second output, the second register .ch connected to STOpBiviH Yehola: N elements And the third to the fourth group, the input of the unit is connected to the third inputs of the second and third groups and the input of the Hi-, zkhod which is connected to the third entrance elgm &: cht AND fourth group,

Ne FIG. Is a structural frame of a controlled random number hecker; Fig 2 is a functional diagram of the analysis block; On the f. G functionally, the generator diagram is -; -;: TOE pulse; in fig. 4 - greasy ;; -: charts of the operation of a controlled random number generator ..; in fig. 5: wooch-; nneHel atroxime ;; -; jfixed pixi The controlled generator contains the first 1 memory, the first deci fraction 2, the memory block 3, the 4 clock pulse generator, the second memory register 5, the compare block 6, the code analysis block 7, the generator of evenly distributed random numbers, the first block of 9 elements And, the element OR 10, the counter 11, the second decoder 12, the third register 13, the second block 14 of the elements And, the inputs 15 and 16 of the generator and the output 1.7 generator. The output of the first register 1 is connected via the first decoder 2 to the first input of the memory block 3, the first, second and third outputs of which are connected to the first inputs of the register 5 to 5 and 1 and the analysis block 7, respectively. The first, second, third and fourth inputs of the generator 4 clock pulses are connected to the first 15 and second 16 inputs of the device, the last output of the second decoder 12 and the second output of the analysis unit 7, respectively. The first output of the 4 clock pulse generator is connected to the first input of the counter 11 and to the third input of the second block 14 of the I- elements, the first and second inputs of the block 14 are connected to the output of the register 13 and to the second output of the generator 8 of uniformly distributed random numbers, respectively the output of the block 14 is connected to the output 17 of the device. The second output of the generator 4 clock pulses is connected to the second inputs of registers 1 and 5, the 3 unit of data and the analysis unit 7, the first output of the analysis unit 7 is connected to the fourth input of the register 1. The third output of the generator 4 is connected to the third input of the comparison unit 6 , the first two groups of inputs of which are connected respectively with the first group of outputs of the generator 8, with the outputs of the register 5, and the output of Equation 6 is connected to the third input of the analysis unit 7 and to the first input of the element OR 10. The fourth output of the generator 4 clock pulses is connected tothe generator 8 evenly distributed random numbers, the first group of outputs of which is connected to the first group of inputs of block 9, AND, the second group of inputs of block 9 is connected to the outputs of the decoder 12, and the outputs of block 9 are connected to the second group of inputs of the element OR OR 10 is connected to the first input of the register 13, the second input of which is connected to the seventh generator output of 4 clock pulses, and the fifth and sixth outputs of generator 4 are connected to the second inputs of counter 11 and decoder I. respectively The third register input 1 connected to the last output of the decoder 12, the inputs of which are connected to the outputs of the counter 11. The analysis unit 7 (FIG. 2) contains a two-charge memory register 18, a block of 19 AND elements, an HE element 20, an OR 21 element, inputs 22-24 and outputs 26 and 25, with the first and second groups of inputs of the register 18 connected respectively to the inputs 22 and 23 of the analysis unit 7, and the output 24 of the unit 7: connected to the third input of the elements I 1E and 19z and to the input of the element HE 20, the output of which is connected to the third element input 19d, the first output of the first bit of register 18 is connected to the first inputs of the element Commerce And 19 and 19, and the second output of the first bit of the register 18 is connected to the first inputs of the elements And 19d. and 19, the first output of the second bit of the register 18 is connected to the second inputs of the elements AND 19 and 194, and the second output of the second bit of the register 18 is connected to the second 1M inputs of the elements 19 and 19, the output of the element I 1 is connected to the first output 25 of block 7 analysis, and the outputs of the elements And 19, 19 and 19 through the element OR 21 connected to the second output 26 of the block 7 analysis. The clock pulse generator 4 (FIG. 3) contains AND 27 and OR 28 elements, triggers 29, pulse generator 30, trigger 31, HE element 32, AND block 33, inputs 1516, 34 and 35, and a group of outputs 36, the first and The second inputs of the pulse generator 30 are connected to the first 15 and second 16 inputs of the device, respectively, and the first output of the pulse generator 30 is connected to the second inputs of And 33, 332, 334. and 335, the second inputs of And 33j and 33, seventh output 36- , the generator 4 clock pulses, the second and third inputs of the trigger 29 and the second input of the trigger 31 are connected to the second m output of the pulse generator 30, the third 34 and fourth 35 inputs of the generator 4 are connected respectively with the first and third inputs of the trigger 31, as well as with the first inputs of the elements OR 28 and AND 27, respectively, the first output of the trigger 31 is connected to the third input of the element And 33, to the first inputs of the elements AND 33 and to the second input of the element AND 27, the output of which is connected to the second input of the element OR 28, and the output of the element OR 28 is connected to the first input of the trigger 29, the second output of the trigger 31 is connected to the first input of the element 33, and the first inputs elements and 33 and 33d with dineny yield-flop 29, and output element 33 through the NOT element 32 is connected to first element vhotsu, and 33, the block 33 outputs the elements K are connected to corresponding outputs 36 yuschimi generator 4 -takt O pulses. Managed random number generator works as follows. Obtaining random numbers (il p) with a given distribution law F {x) is based on comparing uniformly distributed random numbers taken from the output of generator 8. with values of F (k} and finding the interval where the condition p / V is satisfied - - IV 1 t When a number falls into the interval / F (X, -); F (.), The controlled generator outputs the number x., Subject to the law F (x). We assume that the values of the function F (3 x,), and register 1 contains the address of the memory location in which the value of the function F (x) is stored at X 0.5. When a signal is received La Start at input 15 starts the generator of 4 clock pulses, which produces a series of pulses controlling the operation of the device (FIG. 4). By the signal from the first output of the generator 4, the counter 11 is set to S the initial state, and by the signal from the second output The clock generator reads the first word from memory block 3 and takes it back to registers 1 and 5 and analysis block 7. At a signal from four. With the output of generator 4, the generator starts with 8 uniformly distributed random numbers. Each word, stored in the keypad; o2 device 3, consists of three parts: in the higher bits, the word for the scribe is the value of the distribution function F (x :), and in mA, D1g: their bits are cell address mi ti p which is stored the next word and two-digit dL code Z,. When reading the next word from memory B, the address register enters the alres of the next word, in pet-KCTp 5, the value of the function F; x. and in Analysis Block 7, a code that is read from the memory of the first word & Register 5 receives the value P (x = 0.5), which at the time specified by the signal from the third generator output, 4 clock pulses, is compared in block 6 with the number s, removed from the generator output. 8 uniformly distributing random random numbers. If F (x,;) r, a single signal () is generated at the output of the comparison circuit, otherwise it is zero). The signal L from the output of the comparison circuit enters the analysis block 7, and through the element OR 10 is recorded in the lower bit of the register 13. At this, the formation of the high bit of the random number ends. Further operation of the generator depends on the value of the code Z .; received in the previous cycle in the register 18 of the analysis block 7, the scheme of which is shown in Fig.2. In this scheme, the first group of inputs is 22; unit 7 is connected to the third group of outputs of memory unit 3. Therefore, the code Z. from the storage device 3 is recorded in the register 18 at the times specified by the control signal received at the second input 23 of the analysis unit 7. The signal L from the output of the comparison circuit 6 is fed to the third input 24 of the analysis block 7 ,. The first output 25 of the block 7 is connected to the input of the unit in the low-order state of register 1, nosTOf iy, if the first output 25 of the analysis block 7 is formed the signal in the low bit of register 1 is written to one, otherwise the previously recorded value is saved in this bit. Consider the operation of a controlled random number generator with, - 00 using the example of the formation of r.e.er and the number x. On the campaign of element 192 (i.e., on the first E 25th exit of block 7), a single signal can only be written with and, since the outputs of the element E 1 5 ;, the connection; {s with second. red (inverse) outputs ps :: - Jgpa 18 and with the third input of the block. Therefore, with output 25 of block 7 of the circuit, a single signal is generated and D is the smallest register 1 record:; wastcr unit. According to the register 1, which is generated in such a way E., of the 1 kz of memory, the word is read, the most significant bits of which contain the value of the function F (, 75). Here A ,, is the code stored in (1.) senior: register bits one; (f is the bit size of the register 1; A is the executive address. If bL is O, a zero signal is formed at the output 25 of block 7, and the zero value is stored in m fallen de reg register 1, i.e. The second digit of the number at the address in the memory stores the word, in the higher bits of which the knowledge F of the function F (.25) is written. Thus, it turns out that, depending on the value of b.; -: the memory reads either the value functions F (, 25), or F (, 5 ;, Since at F (x 0, -5), then in this case the value of F is read from the memory (,, 25), i.e. value- :: functions F (x) on the middle imt (pbaa OixsO, 5, If (, 5), then the value of the function F (x) is read from the memory at, 75, i.e. at the argument value, in the middle of the interval 0, in the same way the formation of and selecting the median values of the function F (x) and forming the remaining bits of the random number if. A random number is formed in the shift register 13, in mill: the lower bit of which, by the output of the comparison block b, a unit is written if F (), and zero otherwise. The shift towards the higher bits before the 15 bits of numbers formed is carried out in register 13 according to the signal from the seventh output of the generator 4 clock pulses.

Consider the operation of a controlled 20 random number generator with. In this case, the operation of the generator depends on the value of the signal q generated at the second output 26 of the analysis unit 7. If, the formation of the most significant bits of the number k is completed, and the lower bits of the number X., starting from the next, clock cycle with a probability of 0.5, units are recorded. The signal q is formed at the output of the element OR 21, the inputs of which are connected to the outputs of the elements to 19., 19-3, and therefore the signal q is equal to one if il z Z 11 and b 1, or 01, and 35, B other cases x / cm. block diagram 7, shown in Fig.2),

The signal q is fed to the fourth input 35 of the generator 4 clock pulses, the circuit of which is shown 40 in FIG. In this scheme, the pulse generator 30 forms on the first and second outputs continuous sequences of clock pulses, which follow with the same frequency and are shifted relative to each other by half the period. Therefore, the operation cycle of the proposed generator consists of two micro-tacts. Before entering signal 35 of generator 4, signal 50, generator 4 in each cycle (except the first) in the first micro tact generates signals on the second 36 and fifth 365 outputs, and in the second micro tact - signals on outputs 36 and 36-. jj In the first cycle of each cycle, all the named signals are formed with the exception of the signal at the fifth output. In the first cycle, the signals are also formed on the first 36 and fourth l ZD of the outputs of the generator 4 (see the time diagram shown in figure 4). The signals from the second output of the generator 4 are used to read information from memory block 3 and receive it in registers 1 and 5 and in 5

analysis unit 7. According to the signals from the third and fourth outputs of generator 4, the comparison unit 6 and the random number generator 8 are activated, respectively. To increase the content of the counter 11 by one and shift the contents of the register 13, control signals are used that are generated at the fifth and seventh outputs of the generator 4 clock pulses, respectively. The signal from the first output of the generator 4 is necessary for setting the counter 11 to the initial state and issuing the random number generated in the previous cycle to the output 17 of the generator. All of these signals are generated by generator 4 in both the case and in the case of Z 00 at. Note that in the case of Z., the signal at the first output of the analysis block 7 is always zero and, consequently, the executive address A is equal to the address supplied to register 1 from memory 3. Therefore, in this case, it is possible to switch to reading only one node F from the memory ( ), and not the choice of one point of the two, as in the case of Z - 0 €. When a signal arrives at the fourth input of the generator 4 clock pulses, the trigger 29 goes to one state, and the trigger 31 goes to zero. We assume that the scheme uses two-step synchronous 1K-flip-flops, to the second input (synchronization input) of which a signal is received from the second output of the generator 30 (FIG. 3). Therefore, the triggers 29 and 31 change their states on the falling edge of the pulse removed from the second output of the generator 30, thereby allowing the appearance of pulses on the fourth 36 and sixth 36g outputs of the generator 4. At the same time, the passage of signals to the first 36, second 2 and third 36. outputs of block 4 is prohibited. In the next cycle, the signal from the second output of the generator 30 triggers the 29 returns to the zero state, prohibiting the pulse from passing further to the fourth output of block 4. Therefore, after the signal arrives at the fourth 36 output of block 4, only one pulse can appear, which will start the generator 8 evenly distributed random numbers.

Interrogation of generator bits 8 takes place on signals from outputs of decoder 12 at time points, set by signals from sixth generator output 4. The stream of pulses generated from generator outputs 8 through OR 10 input is fed to input of low-order shift register 13. Thus, after completing the formation of the next random number in the lower bits of the register 13, there is a code, the probability of occurrence of a unit in the bits of which is 0.5.

The formation of the next random number ends at that moment in time when the counter 11 n-goes to, (t-1) -th state and at the last output of the decoder 12 a pulse is sent in / out, which sets in register 1 the starting address - the address of the memory cell and in which the value of F (, 5) is stored. Here is the t-rank of the random number x. The pulse from the last output of the decoder 12 also enters the third input 34 of block 4 and converts the triggers 29 and 31 into a single connection, thereby prohibiting the passage of the signal to the sixth output 36 of the generator 4, since the first input of the And 33g element is connected to the second (inverse) trigger output 31, and allowing signals from the output of generator 30 to the first 36, second Zb2, third 36 and fourth Zbd outputs of block 4, since in the next cycle the signal from the second output of generator 30 pulses trigger 29 returns to the zero state, and trigger 29 is connected to first inputs of AND gates 33 and 33j, to the first 36 and fourth 36 extends unit 4 outputs only one pulse. The pulse from the first output of block 4 is set to the initial (zero) state of counter 11, the random number x generated from the previous cycle is read from register 13 and the next random number is started to form. If necessary, the size of the generated random numbers can be increased by adding to the number of a uniformly distributed number from the generator 8 (the generator outputs 8 through the elements ii 14 are connected to the outputs 17 of the device). Since the first input of the element AND 33. through the element NOT 3.2 is connected to the first output 4, then the fifth output 36. the signal "can appear only at times when there is no signal at the output of the element 33. The seventh output of the block 4 is connected directly to the second output of the generator 30, so the signals at the output 36 of the generator 4 appear in each cycle.

The above described sequence of work cycles for generating random numbers x continues to

until the Stop signal arrives at the input 16 of the generator 4. When this signal arrives, the pulse generator 30 stops forming pulse sequences and the operation of the controlled random number generator ends there.

The way to increase the reproduction accuracy of the distribution F (x) is to increase the number n of the approximation intervals due to the shorter length h of these intervals. The resulting error in the approximation of the function F (x) in the case of piecewise linear interpolation is determined by the well-known Newton formula

e 1; | rchc) | lls, ks,

where h

- the length of the 1st section of the approximation; ) / MCiKc-- module value

the second derivative of the function F (x) B to the point m, where the approximation error is maximal,

In the known device, the range of values of the argument x is divided into n equal intervals, the length of which, in the case of formations, is xel X .. is equal to where m is the rarg-distribution of numbers. At the same time, the number of approximation areas is determined by the formula n l / h 2. Thus, with an increase in the size m of the formed numbers, the reproducibility of the distribution of the distribution Fix) decreases due to a decrease in the length h y iA of the approximation, i.e. by increasing the number of approximation nodes F ().

Since the storage of the nodal points F (x.) Is necessary to use a storage device with a capacity of n-1 numbers, this method of improving the accuracy of reproduction is associated with significant hardware costs. Indeed, the increase in the size of the formed numbers always by one bit requires a doubling of the storage capacity of the memory device, “Since the number n of approximation areas doubles.

The proposed device implements a method for obtaining random numbers x, based on a piecewise linear approximation of the distribution function F (x) by dividing the range of the values of the argument x into n unequal differential values. The length h of each interval is selected in such a way that the approximation error does not exceed a specified value. Therefore, in those areas where the modulus of the second derivative IF (f) increases, the length h (interval) should be reduced, and if | P () decreases, the length h can be increased. The graph in Figure 5 illustrates the approximation of a given distribution F (x). When forming the first digit of a number, a uniformly distributed random number is compared with the value F (, 5). (x 0.5 then the generated number x can take a value from the interval 0, if (, 5), then the number x turns out to be c in the interval, 5. When forming the second bit, depending on the result of the first test, the number is compared or with the value F (, 25). if x, - € {0,0, 5), l bo with the value F (, 75) if (O, 5,1). The process of comparing H with the median values of the function F (x) continues until the interval ц F (Xj) (),. (2) falls within. However, by dividing the range of changes into n unequal numbers,% can fall into interval (2) not for m steps (as in the known device), but earlier. Here m is, as before, the size of the generated numbers X, Пример Example 1. nycTb 7 / F (, 75) Then, due to the monotonicity of the function F (x), we have 7F (, 5) and, consequently, as a result of the first test, we obtain that (0 , 5; 1). In the second step (cycle), the number is compared with F (, 75), with the result that we get (0.75; 1). Since there is no further breakdown of the interval (0.75; 1) populations in this case (Fig. 5), the generation of the next number (the missing t-2 digits of the number x are removed from generator of uniformly distributed random numbers). Thus, in the considered example, two high-order digits are formed in two cycles, and in the lower-order digits, starting from the third, with a probability of 0.5, units are dropped (in the proposed device, the two higher-order digits are formed using the comparison circuit, and bits - by polling the values of generator bits 8 decryptor 12 and then putting the result in the lower bit of the shift register 13, the contents of which are shifted by one bit in each cycle). Example 2. Let F (): F (). Then the interval (3/16 1/4) to which the generated number should belong will be found in four steps (in the first clock) compared with F (, 5), in the second with F (), in the third with F (), in the fourth - with F (). Thus, depending on the value, the search for interval (2) occurs in K steps (cycles), where K is a random value, less than or equal to m. Therefore, a device implementing the considered method of generating random numbers x must function in such a way that at each step, it was determined whether the number fell into the interval (2) or not. For this purpose, the proposed device contains an analysis unit 7, which determines. the moment the numbers hit the interval (2). When the interval (2) enters the analysis block 7, it generates a signal and the proposed generator switches to the low-order bits of the output register 13 with a probability of 0.5 single signals. After completing the formation of the t-bit random number X, the signal from the last output of the decoder 12 generator proceeds to form the next random number, and the number x formed in the previous cycle, from the outputs of the register 13 and generator 8, through the block 14 of the elements I, is fed to output 17 of the device. In order to determine when a number falls into the interval (2) in the storage device 3, not only the values of the function F () and the addresses of the following nodal points, but also the two-digit code Z are recorded during the period of tuning the generator to implement the specified distribution law. This code is in each clock cycle enters analysis block 7, which, depending on the value of Z and the value of the signal L from the output of the comparison circuit 6, forms the signal q. . In the proposed device, it is assumed that, with Z.00, the generator forms the next bit of the number x in the usual way, i.e. after dividing the next interval in half and comparing with F (x) in the next clock cycle, both received half-intervals are divided in half, and the node point is selected depending on the value of the signal b: the function value calculated in the middle of the left half-interval is read from the memory, and - in the middle of the right half-interval. Admission to the unit 7 analysis code, yes means that the desired engine. The interval (2) is found and the generator, beginning with the next clock cycle, according to the signal formed in block 7, forms the remaining minor bits of the number x, bringing in the register 13 equal binary signals. Obviously, such a case is possible when all m bits of a number are formed using a comparison circuit. In this case, the determination of the moment of entry into the desired interval occurs by the signal from the last output of the decoder 12, and the formation of the signal is blocked by entering the code analysis from block 7, thereby excluding the possibility of entering into equal binary signals to the lower bits of the register 13.

When the generator is in operation, it is possible that, after dividing the next interval in half into the next cycle, it is necessary to halve only one of the two half-openings obtained. For the purpose of determining the half-interval to be divided, the following control signal values are entered: and. If Z.01, in the next cycle, only the right half-interval is divided in half, and when hit, the left-open half-interval not to be divided (i.e., in) in block 7 a signal is formed and the generator proceeds to form lower-order digit digits. If, in the next cycle, the left half-interval is divided in half, and on hit. in the right half-interval (i.e., at)

From a comparison of the tables it can be seen that the proposed device, depending on 60 On the size of the generated numbers, allows to reduce the memory size by 2.1-2.9 times while maintaining the accuracy of 6 approximations. Reducing the amount of memory also leads to a reduction in size.

in block 7, a signal is generated. Therefore, the analysis unit 7 generates a signal not only at, but also at Z 01, if, and at Z 11, if.

Thus, the proposed generator makes it possible to reproduce a given distribution F (x) when the region X is divided into n unequal intervals, whether the condition (2) is satisfied in each clock cycle or not. Since, in the known device, the detection of the moment of falling into the interval (2) occurs only in the tth cycle, the known device does not allow dividing the range of values to into n unequal intervals, and therefore, requires additional memory to achieve the same accuracy characteristics. / which has the proposed device.

In order to compare the accuracy characteristics of the proposed device and the known one, formula (1) was used to calculate the approximation error of the exponential distribution F (x) l -exp (-X x) for L 8. Tables 1 and 2 show the error values obtained approximations and memory size N depending on the size m of the generated numbers x. The amount of memory is determined by the DTS; according to the formula N p-1, where n is the number of approximation intervals that provide accuracy,. Table 1 shows the characteristics of the known device, and Table 2 shows the character ;; sticks of the proposed device.

Table 1

table 2

Registers 1 register and the number of outputs of the decoder 2.

Claims (1)

1. USSR author's certificate No. 213424, cl. G About F 1/02, 1966. USSR certificate 06 F 1/02, 1969. USSR certificate 06 F 1/02, 1971 63 .-Ll