JPS6084017A - Pll circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for an LPF, to attain a high speed response and also to obtain a high stability by controlling a voltage controlled oscillator (VCO) with three output levels of a phase comparator so as to bring a PLL circuit into the phase lock state. CONSTITUTION:An external input rectangular wave signal (a) is applied to a monostable multivibrator MM13 from a terminal 5 and the MM13 supplies a pulse (b) of a pulse width TW to a phase comparator PD12. The PD12 outputs a high level VH or a low level VL when the output of the MM13 is at a high level, and the PD12 outputs a middle level VM when the output is at a low level. The VCO3 oscillates three kinds of frequencies FL, FM and FH respectively in response to the three kinds of the output levels VL, VM and VH of the PD12. If there is a phase difference between an output signal of a frequency divider 4 and the external input rectangular wave signal, the ratio of a period TH when the PD12 outputs the VH in the TW to a period when the VL is outputted is changed, and the phase of the output signal of the frequency divider 4 is controlled so that the phases are made coincident. The output of the PD12 is the VM at periods other than the TW and the oscillated frequency of the VCO3 is an FM.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an improvement in a phase-locked loop, a so-called PLL circuit, for obtaining an oscillation output that is phase-locked with an input signal.

<Description of Prior Art> Conventionally, analog PLL circuits and digital PLL circuits have been frequently used in various devices. It was unsuitable for specific applications requiring high stability. Hereinafter, this point will be explained in detail using the drawings.

FIG. 1 is a diagram showing a general configuration of a conventional PLL circuit. In FIG. 1, 1 is a phase comparator (PD), 21
Low pass filter (LPF) as loop filter of riPLL circuit, 3Vi% as pressure controlled oscillator (VCO)
, 4 is a 1/n J'fR device, and 5 is a terminal to which an input signal is supplied. Phase comparators 1 are generally classified into analog and digital types, and PLL circuits are accordingly classified into analog PLL circuits and digital PLL circuits.

First, the conventional analog I)LL circuit 1 will be explained. FIG. 2 is a diagram showing the main part configuration of an example of a conventional analog PLL circuit. In the figure, 6 is a waveform shaping circuit and 7if multiplication circuit, which constitute a phase comparator. Referring to FIG. 1, the phase comparator 51 is constructed at 6°7.

2a is an LPF, which corresponds to LPF2 in FIG. Further, 8 is a terminal to which a rectangular wave for phase comparison is supplied as the output of the l/n frequency divider shown in Fig. 1, and 9 corresponds to terminal 5 in Fig. This is a terminal to which a rectangular wave signal (for example, a horizontal synchronizing signal of a television signal) is input as a narrow pulse with a duty of 50 or less. 1O is an output terminal that supplies an output signal to the VCO 3 shown in FIG. 1, Vcc is a terminal to which a power supply voltage is applied, and a terminal to which a null bias voltage is applied.

FIG. 3 is a timing chart showing waveforms at each part of FIGS. 2(a) to 2(e), and the operation of the circuit shown in FIG. 2 will be described below. 1/n frequency divider 4 input to input terminal 8
The phase comparison rectangular wave (a) of An external input rectangular wave signal (C) is supplied, and a part of the above-mentioned sawtooth wave (b) is extracted by the external input rectangular wave signal (C) by multiplication in a multiplier 7K.
d).

This extracted signal (d) is passed from the external input signal (I) to the LPF2aK as a loop filter made of C.
Only the low frequency component corresponding to the phase error between C) and phase comparison rectangular wave (a) is eliminated, and when the oscillation phase of VCO3 is delayed by the control S++ signal (e), the oscillation frequency of VCO3 increases. When moving in the direction, is the oscillation frequency suppressed in the direction of decreasing? It is shouted.

Therefore, the VCO 3 is always controlled in a direction that reduces the phase error and is phase locked.

Now, in the analog PLLN path as described above, the VCO is controlled over the entire period, but since the phase shift is detected at a predetermined period, the information on the phase shift is
It takes a certain amount of time for it to be reflected in the CO control.

This means that the response speed of one LPF 2a determines the response speed of the entire I) L L circuit. The response of the PF2a becomes a problem in one component of the high-speed response PLL circuit. That is, for example, if the frequency of the external input rectangular wave signal is 15.734 KHz (horizontal synchronization frequency of the television signal), the LPF 2a will fully eliminate 15,734 Kl (z component and related components) of the output of the multiplier 7. Therefore, the cutoff frequency must usually be set to a number of 1001-12.This makes high-speed response difficult.In this 4'!11 analog PLL circuit, In this case, it is possible to attenuate the frequency component of the external input square wave signal by sampling and holding the output of the multiplier 7, but even in this case, if the frequency of the signal is 1, then l
/fT (63.55 when fT=15.734KHz
6 μfi), it was not possible to expect a significant improvement in the response due to the deterioration of the frequency characteristics associated with the current. Also, when considering stability,
' and the phase delay associated with sample and hold would impair stability.

Next, a conventional digital PLL circuit will be explained. FIG. 4 is a diagram showing an example of the configuration of a conventional digital PLL circuit. Components in FIG. 4 that are similar to those in FIG. 1 are designated by the same numbers. Reference numeral 11 indicates an ant game), and reference numeral 2b indicates an LPF corresponding to LPF2 in FIG. Figure 5 (A)
.

(B) and (C) are timing charts showing the waveforms of each part in FIGS. 4(a) to (d), and the operation will be explained below.

Figure 5 (A) shows a state in which the PLL1 path shown in Figure 4 is phase-locked, and Figure 5 (13) shows a state in which the frequency is divided compared to the external input rectangular wave signal (a) for some reason. Output of device 4 (b
) shows the state when the phase advances.

As is clear from the figure, when the phase of the output signal of the frequency divider 4 advances, that is, when the phase of the signal oscillated by the VCO 3 advances, the output pulse of the AND gate ti (
The pulse width of C) becomes narrower, and the control voltage (d) supplied to the VCO 3 becomes lower. Therefore, the oscillation frequency P of the VCO 3 becomes low and the phase of the signal oscillated by the VCO 3 is delayed. As a result, the phase lock state as shown in FIG. 5(A) is drawn.

FIG. 5(C) shows a state when the phase of the output signal (1) of the frequency divider 4 is advanced compared to the external input rectangular wave signal (a). In this case as well, as is clear from the figure, when the phase of the output signal (b) of the frequency divider 4 advances, the pulse width of the output pulse (C) of the anti-gear 11 becomes wider than when the phase is locked, and is supplied to the VCO 3. The controlled voltage (d) increases. Therefore, the oscillation frequency of the VCO 3 also increases, and the phase of the signal oscillated by the VCO 3 advances, leading to a phase locked state.

Even in the digital PLL circuit described above, since the VCO is controlled over the entire period, a smoothing means such as an LPF must be used.
Similar to the circuit, a response delay occurs, and it is extremely difficult to construct a high-speed response PLL circuit. The stability of the PLLM path due to the delay in response also deteriorated.

<Objective of the Invention> The present invention provides a PLL circuit that is capable of high-speed response and has high stability by eliminating the problems related to high-speed response and high stability in conventional PLL circuits as described above. With the goal.

<Explanation of Examples> The present invention will be explained in detail below using examples.

FIG. 6 is a block diagram showing the configuration of a PI/I/circuit as an embodiment of the present invention. In Figure 6, 3 is VC
014 is a frequency divider, 5 is a terminal to which an external input rectangular wave signal is input, 12 PIs capable of outputting three levels of high level, low level and intermediate level), 13 is a mono multivibrator (MM). Figure 7 (A), (H)
, (C) U FIGS. 6(a) to 6(d) are timing charts showing waveforms of each part, and the operation will be explained below.

The external input square wave signal (a) is input from terminal 5, and MM
13. MM13/'i A pulse (b) having a pulse width Tw (shown in FIG. 7) is supplied to the PD12.

As the other input of the PI) 12, the output (C) of the frequency divider 4 which has counted down the oscillation output of the VCO 3 to 1/n is input as a comparison signal, and phase comparison is performed here.

Here, the operation of the PD 12 will be explained. PD12 is M
Only when the output of M13 is high level is the high level (Vn shown in Figure 7) still low level (@V shown in Figure 7).
), and when the output of MM13 is low level, it outputs an intermediate level (vM shown in FIG. 7). Furthermore, when the output of MMt3 is at a high level, that is, during the - period, the PD12 whose output from the frequency divider 4 is at a high level outputs v5, and when the output of the frequency divider 4 is at a low level, PD12 outputs VH. .

PD12 output (d) ijiiim Send to VCO3 h, VCO3 Ha PD12 output L/to #V
h-VM, FI, FM, respectively depending on Vi Ic.
It oscillates a frequency of 3rd or 4th class called Fat. The oscillation output is supplied to the l/n frequency divider 4, where the frequency is divided into 1/input and then supplied to the comparison input terminal i of the PD 12, forming a closed loop.

Now, if for some reason the phase of the output signal of frequency divider 4 is delayed compared to the phase of the external input rectangular wave signal, then
As shown in Figure (B), within the aforementioned period 1'vI, PD
The period during which t2 outputs VH (indicated by TH in +<41) is longer than the period during which t2 outputs vL (indicated by TL in the figure). Therefore, the period in which the VCO 3 oscillates at the oscillation frequency FH becomes longer than the period in which it oscillates at FL. In this case, the output signal of the frequency divider 4 is controlled so as to advance in phase. On the other hand, if the phase of the output signal of the frequency divider 4 is delayed compared to the phase of the external manually input rectangular wave signal, then As shown in Figure 7 (C), within Tw, TL becomes longer than T, and VCO3 becomes FL
The period of oscillation at FH is longer than the period of oscillation at FH. Therefore, in this case, the frequency divider 4 is controlled so that the phase of the output signal is delayed.

In periods other than l11w, the output of PD12 is rice, and the output of VCO3 is 9? , the vibration frequency is FM.

The divider 4 is an l/n frequency divider, and is selected so that FMld: n1tR is obtained, where the frequency of the externally input rectangular wave signal is FR. Therefore, during the period below 1, the VCO 3 essentially free-runs and is not controlled.

Also, of course, from F+i Id Fpa, B < F
1.17J, which is a lower frequency than F'M.

When the PLL circuit becomes a phase-locked vibrator due to the above-mentioned action, 1, for example, 1゛1 (and +
1+L both become %1゛w, and the phase lock state is maintained. As mentioned above, the ratio of TH and 'vL (however, 11゛L
-'l'w), negative feedback I'LL is constructed.

The operation of the PLL circuit described above will be analyzed below.

Now, assuming that the voltage-frequency characteristic of VCO3 is F = kV (1), it becomes as follows. Also, the output signal level of PL) 12 is ~'H+
If the periods of the output signal oscillated by the VCO 3 when v■ and 1■M are respectively τH1τL and τM, then the following equations are obtained.

Now, the period corresponding to the generation cycle of the external input square wave signal is T
o (shown in Figure 7), the period during which the output signal level of PD12 is high is TM, and pLr is the number of pulses generated by VCO3 at T, , TL, and +v when the circuit is phase-locked, respectively. , l+, m, PL
The L circuit is phase locked.1. If T,, =
Since TL='rw/2, it becomes. However, l + h + m = n' (5).

Also, when the PLL circuit deviates from the phase lock state and the phase of the output signal of the frequency divider 4 advances by △t from the phase lock position, T□=TL, TMic The number of pulses generated by the VCO3 is l' and h', respectively. , m', then it becomes. On the other hand, the period (To) corresponding to the period of the output signal of the time frequency divider 4 is 'l'o'-J'i, 'L+h'T1(+m'Tg (
It is 71. (Substituting equation (6) into the force equation and using the relationship in equation 3), “””(/+△tFL) τI, +(h-ΔtF1)T
ii + (n - (7? + ΔtpL) - (h - Δt F'
R) )τM=lτb+h′rH+(n −/−h)r
g1Δ'FLrL-△tF Hr Hl -△t, F
L r M 10△tF u ”M (8). By the way, since irL + hrH + mrH = T□ (9), To' = To + △tτM (FH - FL ) Q (1, so we get. To is PLL Since this corresponds to the period corresponding to the period of the output signal of the frequency divider 4 when the circuit is phase-locked, the time 'Ill loop gain ('
-'t)/'i becomes 1 time axis dynamic range (,D,)r,J:
becomes.

You can choose a loop gain as large as you like by setting FH-FL to a large value, but in reality, it is
PL=I MHz %F, about -7Ml-1z is appropriate. At this time, the loop gain I'i is 1.5. )
Next, the general circuit configuration of the PLL circuit that performs the above-mentioned a-opening operation will be explained. Figure 8 shows P in Figure 6.
It is a figure which shows the concrete example of a circuit of D12. In Figure 8, 14. 〜几1. are resistors, 01 to C7 are capacitors, DI~1]4 are diodes, Ill, ~Il, respectively.
+ and 21 are transistors respectively, and 21 is MM1 in FIG.
22t is a terminal to which the output signal of frequency divider 4 is supplied, 23 is a terminal to which power supply voltage Vcc is supplied, and 24 is a terminal that outputs a control voltage to be supplied to VCC3.

In this configuration, when the output of MM+3 is at a low level, the transistor Tr is turned off, so the transistors 'lr, t'lr, and l are also turned off. Therefore, transistors l1lr4. Ill and Tr are also turned off. Now, assuming that the resistance values of the resistors 1, . Next, the output of MM13 is high level, and the frequency divider 4
When the output of transistor Tr and l1 is also at high level,
lr, turns on. Therefore, the transistor Tr is turned on, and thereby the transistor Tr6 is also turned on. On the other hand, since the transistors Tr and u are off, the transistor Tr is turned off.

Therefore, a voltage at a lower level than the above-mentioned %Vcc is output to the terminal 24. However, the voltage at terminal 24 is limited to % because the amplitude is limited by a limiter consisting of diode D9゜D4, resistor 1 (1, 4, R1, and capacitor CIl).
Vcc - VO2 (however, VO2 is diode D4
forward voltage). Furthermore, when the output of MM13 is at the no-no level and the output of the frequency divider 4 is at the low level, the transistor Tr
, , Tr, is on and transistor Tr is off, resulting in transistor l1lr.

is turned on, and the t-run lister Tllr is turned off.

Therefore, a voltage at a level higher than the above-mentioned %Vcc is outputted to the terminal 24. However, since the amplitude is similarly limited by the limiter mentioned above, the resistance pressure of terminal 24 is 3A VCC+
VO3 (VO3 Hatao-)” Ds(r) Ill
direction voltage).

In this way, by appropriately determining the resistance value of the resistor L (, 0 to 1 mo, 5) and the forward voltage of the diode D, D4 in the configuration shown in FIG.
A PD that outputs three levels of L is obtained.

According to the PL and L circuits explained above using FIGS. 6 to 8, vC at the three output levels of the phase comparator as described above.
It is possible to control O and bring the PLL circuit into a phase-locked state. Therefore, the loop LPF, which is naturally necessary in conventional PLL circuits, becomes unknown, and the response speed is determined by this LPFK. Never. Therefore, a PLL circuit capable of extremely high-speed response is obtained. Furthermore, since there is no LPF, there is no band limit, and the same loop gain can be obtained in almost all bands, making high-speed response possible. Furthermore, FiL
Since there is no PF, there is no transient response and the PLL is highly stable.
It is what makes up the circuit.

FIG. 9 is a block diagram showing the configuration of a PLL circuit as another embodiment of the present invention. Components similar to those in FIG. 6 are given the same numbers.

PI) 12a outputs a period v corresponding to the amount when the phase of the output signal of the frequency divider 4 is ahead of the external input rectangular wave signal inputted to the terminal 5, and when it is delayed, This is a phase comparator that outputs vL for a period corresponding to the hit, and outputs cat when there is no output of Vu or vL.

Figure 1O (A), (B), (C) and Figure 9 (a)
) to (C) The waveforms of each part are shown, and the operation will be explained below.

Now, when the falling edge of the external input rectangular wave signal (a) and the falling edge of the output signal (b) of the branching device 4 match, the first og
As shown in (A), the output of PD12a is always vM and V
CC3 oscillates near the center frequency and is in a phase locked state.

Next, when the fall of the output signal (b) of the frequency divider 4 is delayed with respect to the fall of the external input rectangular wave signal <a>, as shown in Figure 1O (1
As shown in 3), the output of the PD 12a changes from ``Y'' to Vll at the same time as the external input rectangular wave signal (a) falls, and changes to vM again at the same time as the output signal (b) of the frequency divider 4 rises. Therefore, the period corresponding to the phase delay of the output signal (b) of the frequency divider 4 with respect to the external input rectangular wave signal (a), PD12a
rI′iVu will be output, and during this period VCO3
will oscillate at a predetermined frequency F1 (which is higher than the center frequency. Therefore, the output signal (h) of the frequency divider 4 will lead in phase, and will be i-th.

This is approaching a phase-locked state in which the falling edges of both signals coincide as shown in FIG. 3(A).

On the other hand, when the fall of the output signal (b) of the frequency divider 4 is advanced with respect to the fall of the external input rectangular wave signal (a), Fig. 1O (
As shown in C) (the output of the PD 12a changes from vM to VL at the same time as the output signal (b) of the frequency divider 4 falls, and becomes vM again at the same time as the fall of the external input rectangular wave signal (a). Therefore, During a period corresponding to the phase advance of the output signal (b) of the frequency divider 4 with respect to the external input rectangular wave signal, the PD 12a outputs vL, and during this period the VCO 3 also oscillates at a predetermined frequency F lower than the center frequency. Therefore, the output signal (b) of the frequency divider 4 will be delayed in phase, and in this case as well, the phase lock state as shown in FIG. 10(A) will be approached.

FIG. 11 is a diagram showing an example of a PD circuit for realizing the above-described operation. In Figure 11, 2
1 is a terminal to which an external input rectangular wave signal is supplied, 22 is a terminal to which an output signal from frequency divider 4 is input, 23 is a terminal to which power supply voltage Vcc is supplied, and 24' is a control for controlling vCO. Terminals for outputting signals, 25.26 are D-type flip-flops (DFF), 27B Nant gate, 28 are inverters, 29.30 are husband VOS-FF
XT, R, ~R, , u k resistor, C*ri-r capacitor, I input, and D are diodes and diodes, respectively, and the operation of F will be explained below.

First, let us consider the case where the output signal (b) of the splitter 4 leads in phase to the external input rectangular wave signal (a). Square frequency divider 4
At the falling edge of the output signal of J) FF26 is triggered L.
, the Q output becomes high level, and the Q output becomes low level. Q
The output is inverted from -f inverter 28 and output to MOs-FE'
Applied to r30.

Therefore, at this time, the MO8-FET 30 is turned on, and a low level is obtained from the terminal 24'.

However, the amplitude is determined by the resistances 1-L, 1. Since it is limited by a limiter consisting of It, 4, capacitor CJi and diodes D, , D6, the output voltage is resistor It, , ,
It,.

The voltage is lower than the voltage determined by VD6 (however, the forward pressure of the diode D by 1-'/as). For example, if the resistors It, , )L, and 4 have the same resistance value, then 3AVCCVD6. Thereafter, DFL'' 25 is triggered by the falling edge of the external input rectangular wave signal, and the Q output of I)J''F' 25 becomes high level.

At the same time, the two-man power of the NAND circuit 27 becomes high level, so both FFs 25 and 26 are reset and VOS-
Since FET30 returns to the off state, the output voltage is equal to the resistance It,
Return to the voltage determined by , ,It, .

On the other hand, when the output signal (b) of the frequency divider 4 is delayed in phase with respect to the external input rectangular wave signal (a), Dli'F2 is triggered and its Q output becomes low level. Then i'Ji
When the OS-FET 29 is turned on, as mentioned above, the output voltage from the terminal 24' becomes a voltage higher than the voltage determined by the resistance value of the resistor R7*, "ta" by Vns (
However, VOS is the forward voltage of the diode D. ).

Then, since the DFF 26 is triggered by the falling edge of the output signal of the frequency divider 4, the NAND circuit 27
Study to reach a high level of human power, DFI; '25 and 2
6 is reset (1 output pressure is resistor) L2. ,i(,,
, the voltage determined by 1·ζ returns.

In this way, the circuit shown in FIG. 11 can constitute a PD that operates as described above.

That is, by appropriately selecting the resistance values of the resistors R, , , -1(, 4), it is possible to output the three levels of /V, , VM, and VL mentioned above during the /ζ period according to the amount of phase shift. .

In the embodiments shown in FIGS. 9 to 11 described above, the same effects as in Example 1 shown in FIGS. 6 to 8 described above can be obtained.

Further, according to this embodiment, the dynamic range is 1 greater than that of the previous embodiment.

Historically, vH is 1. When the period during which VD is output is shortened, the wasted time becomes short and it becomes possible to respond at high speed. That is, in the transient state, )/-, b5 has a large dynamic range, and after phase locking, it is a PLL circuit that can respond at the highest speed ever.

<Description of Effects> As explained above, since the PLL circuit of the present invention does not use an LPF, it is possible to configure a PLI circuit that can respond at high speed and has high stability.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the general configuration of a conventional PLL circuit, Fig. 2 is a diagram showing the main part configuration of an example of a conventional analog PLL circuit, Fig. 3Vi Fig. 2 (a) to ( e) Timing chart showing the waveforms of each part, Figure 4 is a diagram showing an example of the configuration of a conventional digital I) L L circuit, Figure 5 (A)
, (B) and (C) are timing charts showing the waveforms of each part of the fourth part, and FIG.
LI, block diagram showing the circuit configuration, FIG. 7(A),
(13), (C) is a timing chart showing the waveforms of each part in FIG. 6, FIG. 8 is a diagram showing a specific circuit example of the PIJ in FIG. 6, and FIG. 9 is a diagram showing another embodiment of the present invention. Example l) Block diagram showing the configuration of the L L circuit, No. 10
Figures (A) and (B). (C) is a timing chart showing the waveforms of each part of the 9th part;
FIG. 11 is a diagram showing a specific circuit example of the main part of FIG. 9. 3 is voltage controlled oscillator, 4-digit l/n frequency divider, 12°128
is a phase comparator, 25.26 digits D F

Claims (1)

[Claims] (1) A PLL circuit including a voltage controlled oscillator and a phase comparison means for controlling the oscillator according to a phase difference between a signal related to the output of the oscillator and an input signal, the phase comparison means comprising: a first predetermined voltage for causing the oscillator to oscillate at a frequency lower than its center frequency; a second predetermined voltage for causing the oscillator to oscillate at a frequency lower than its center frequency; and a second predetermined voltage for causing the oscillator to oscillate near its center frequency. A PLL circuit that selectively outputs a third predetermined voltage as an output voltage.