JPS613520A - Oscillating circuit - Google Patents

Oscillating circuit

Info

Publication number
JPS613520A
JPS613520A JP59124134A JP12413484A JPS613520A JP S613520 A JPS613520 A JP S613520A JP 59124134 A JP59124134 A JP 59124134A JP 12413484 A JP12413484 A JP 12413484A JP S613520 A JPS613520 A JP S613520A
Authority
JP
Japan
Prior art keywords
frequency
signal
oscillation circuit
voltage controlled
frequency divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59124134A
Other languages
Japanese (ja)
Inventor
Yasuta Tomuro
戸室 泰太
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59124134A priority Critical patent/JPS613520A/en
Publication of JPS613520A publication Critical patent/JPS613520A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006Changing the frequency

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)

Abstract

PURPOSE:To attain accurately a duty factor of 50% by providing a voltage controlled oscillation circuit oscillating a signal having a frequency being an integral number of multiple of a desired value and a frequency divider frequency- dividing the frequency of the signal outputted from the said voltage controlled oscillating circuit. CONSTITUTION:A signal outputted from the voltage controlled oscillating circuit 2 is formed to a signal having a frequency twice a desired value and this signal is frequency-divided into 1/2 by the frequency divider 5, then even when the duty ratio of an output pulse 7 of the said voltage controlled oscillator 2 is not 50% but, e.g., T1>T2, a waveform 8 of the signal outputted from the frequency divider 5 frequency-dividing the signal into 1/2 is obtained as T3=T4=T1+T2 and the duty ratio of 50% is obtained accurately.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は出力信号の波形歪を極小とする発振回路に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an oscillation circuit that minimizes waveform distortion of an output signal.

〔従来技術〕[Prior art]

第1図に従来の発振回路を示す。第1図において、1は
発振周波数を制御する電圧を印加するための入力端子、
2は発振周波数を制御する電圧を入力とし発振信号を出
力とする電圧制御発振回路、3は電圧制御発振回路から
出力される信号を外部へ出力するための出力端子である
FIG. 1 shows a conventional oscillation circuit. In FIG. 1, 1 is an input terminal for applying a voltage to control the oscillation frequency;
Reference numeral 2 designates a voltage controlled oscillation circuit which inputs a voltage for controlling the oscillation frequency and outputs an oscillation signal, and 3 designates an output terminal for outputting a signal output from the voltage controlled oscillation circuit to the outside.

このように構成された発振回路においては、電圧制御発
振回路2の回路形式をかなり慎重に選択しても、特に周
波数が高い場合は、第2図に示すように発振回路から出
力、される信号の波形4はそのデユーティファクタが5
0%にならない。このことはその信号が偶数次の高調波
歪を持っていることを意味し、その信号をVTRの映像
変調回路に使用した場合に画質を損なうなどの問題点が
あった。
In an oscillation circuit configured in this way, even if the circuit type of the voltage controlled oscillation circuit 2 is selected very carefully, especially when the frequency is high, the signal output from the oscillation circuit as shown in Fig. The duty factor of waveform 4 is 5.
It won't be 0%. This means that the signal has even-order harmonic distortion, and when this signal is used in a video modulation circuit of a VTR, there are problems such as loss of image quality.

〔発明の概要〕[Summary of the invention]

本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、周波数が高くても信号のデユー
ティファクタを正確に50%とすることができる発振回
路を提供することにある。
The present invention has been made in view of these points, and its purpose is to provide an oscillation circuit that can accurately set the signal duty factor to 50% even at high frequencies. be.

このような目的を達成するために本発明は、発振回路に
、所望値の整数倍の周波数の信号を発振する電圧制御発
振回路とその信号の周波数を整数分の1に分周する分周
器とを設けたものである。
In order to achieve such an object, the present invention includes an oscillation circuit that includes a voltage controlled oscillation circuit that oscillates a signal with a frequency that is an integral multiple of a desired value, and a frequency divider that divides the frequency of the signal into an integer fraction. It has been established that

〔発明の実施例〕[Embodiments of the invention]

本発明を実施例に基づき詳細に説明する。 The present invention will be explained in detail based on examples.

第3図に本発明に係わる発振回路の一実施例を示し、第
4図にその動作を説明するための波形を示す。第3図に
おいて、5は入力信号の周波数を分周する分周器、6は
電圧制御発振回路2から出力される信号を分周器5へ伝
送する伝送線路である。なお第3図において第1図と同
一部分又は相等部分には同一符号が付しである。
FIG. 3 shows an embodiment of the oscillation circuit according to the present invention, and FIG. 4 shows waveforms for explaining its operation. In FIG. 3, 5 is a frequency divider that divides the frequency of the input signal, and 6 is a transmission line that transmits the signal output from the voltage controlled oscillation circuit 2 to the frequency divider 5. In FIG. 3, the same or equivalent parts as in FIG. 1 are given the same reference numerals.

本実施例の発振回路は、電圧制御発振回路2から出力さ
れる信号を所望値め2倍の周波数を有する信号とし、こ
の信号を分周器5で1/2に分周するような構成になっ
ている。このときの信号波形を第4図(a) 、 (b
)に示す。第4図ta+において、7は電圧制御発振回
路2から出力される信号の波形、T1およびT2は高レ
ベルの時間幅および低レベルの時間幅である。また、第
4図(b)において、8は分周器5から出力される信号
の波形、T3およびT4は高レベルの時間幅および低レ
ベルの時間幅である。
The oscillation circuit of this embodiment has a configuration in which the signal output from the voltage controlled oscillation circuit 2 is a signal having a frequency twice the desired value, and the frequency of this signal is divided into 1/2 by the frequency divider 5. It has become. The signal waveforms at this time are shown in Figure 4 (a) and (b).
). In FIG. 4 ta+, 7 is the waveform of the signal output from the voltage controlled oscillation circuit 2, and T1 and T2 are the high level time width and the low level time width. Further, in FIG. 4(b), 8 is the waveform of the signal output from the frequency divider 5, and T3 and T4 are the time width of the high level and the time width of the low level.

第3図および第4図において、電圧制御発振回路2から
出力される信号の波形7が第4図(alに示すようにT
、 >T、となっていても、1/2に分周する分周器5
から出力される信号の波形8、すなわち、この発振回路
から出力される信号の波形は第4図中)に示すようにT
3=Tt=T+ +T2であるためにデユーティファク
タは正確に50%であり、偶数次の歪は発生しない。本
実施例では電圧制御発振回路2の発振周波数が所望の周
波数の2倍の場合について説明したが、任意の整数倍の
場合でもその効果は全く同様である。
3 and 4, the waveform 7 of the signal output from the voltage controlled oscillation circuit 2 is shown in FIG.
, >T, the frequency divider 5 divides the frequency by 1/2.
The waveform 8 of the signal output from the oscillation circuit, that is, the waveform of the signal output from this oscillation circuit is shown in FIG.
Since 3=Tt=T+ +T2, the duty factor is exactly 50%, and even-order distortion does not occur. In this embodiment, the case where the oscillation frequency of the voltage controlled oscillation circuit 2 is twice the desired frequency has been described, but the effect is exactly the same even when the oscillation frequency is an arbitrary integer multiple.

〔発明の効果〕〔Effect of the invention〕

本発明は、所望値の整数倍の周波数の信号を発振する電
圧制御発振回路と電圧制御発振回路から出力される信号
の周波数を整数分の1に分周する分周器とを設けること
により、発振回路から出力される信号のデユーティファ
クタを正確に50%とすることができるので、その出力
信号をVTRの映像変調回路に使用しても画質を損なわ
ないなどの効果がある。
The present invention provides a voltage controlled oscillation circuit that oscillates a signal with a frequency that is an integer multiple of a desired value, and a frequency divider that divides the frequency of the signal output from the voltage controlled oscillation circuit into an integer divided. Since the duty factor of the signal output from the oscillation circuit can be set to exactly 50%, the output signal can be used in the video modulation circuit of a VTR without deteriorating the image quality.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の発振回路の系統図、第2図は従来の発振
回路から出力される信号の波形図、第3図は本発明に係
わる発振回路の系統図、第4図(alはその発振回路を
構成する電圧制御発振回路から出力される信号の波形図
、第4図(b)はその発振回路を構成する分周器から出
力される信号の波形図である。 1・・・・入力端子、2・・・・電圧制御発振回路、3
・・・・出力端子、5・・・・分周器、6・・・・伝送
線路、7,8・・・・波形、TI+ T2、 T3. 
Ta・・・・時間幅。
FIG. 1 is a system diagram of a conventional oscillation circuit, FIG. 2 is a waveform diagram of a signal output from the conventional oscillation circuit, FIG. 3 is a system diagram of an oscillation circuit according to the present invention, and FIG. FIG. 4(b) is a waveform diagram of a signal output from a voltage-controlled oscillation circuit constituting an oscillation circuit, and FIG. 4(b) is a waveform diagram of a signal output from a frequency divider constituting the oscillation circuit.1... Input terminal, 2... Voltage controlled oscillation circuit, 3
... Output terminal, 5... Frequency divider, 6... Transmission line, 7, 8... Waveform, TI+ T2, T3.
Ta...Time width.

Claims (1)

【特許請求の範囲】[Claims] 所望値の整数倍の周波数を有する信号を発振する電圧制
御発振回路と、前記電圧制御発振回路から出力される信
号の周波数を整数分の1に分周する分周器とを備えたこ
とを特徴とする発振回路。
A voltage controlled oscillation circuit that oscillates a signal having a frequency that is an integer multiple of a desired value, and a frequency divider that divides the frequency of the signal output from the voltage controlled oscillation circuit into an integer fraction. oscillation circuit.
JP59124134A 1984-06-15 1984-06-15 Oscillating circuit Pending JPS613520A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59124134A JPS613520A (en) 1984-06-15 1984-06-15 Oscillating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59124134A JPS613520A (en) 1984-06-15 1984-06-15 Oscillating circuit

Publications (1)

Publication Number Publication Date
JPS613520A true JPS613520A (en) 1986-01-09

Family

ID=14877761

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59124134A Pending JPS613520A (en) 1984-06-15 1984-06-15 Oscillating circuit

Country Status (1)

Country Link
JP (1) JPS613520A (en)

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