JPS60190018A - Frequency multiplier circuit - Google Patents
Frequency multiplier circuitInfo
- Publication number
- JPS60190018A JPS60190018A JP4635884A JP4635884A JPS60190018A JP S60190018 A JPS60190018 A JP S60190018A JP 4635884 A JP4635884 A JP 4635884A JP 4635884 A JP4635884 A JP 4635884A JP S60190018 A JPS60190018 A JP S60190018A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- waveform
- wave
- frequency
- distortion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は人力波の逓倍波を得る周波数逓倍回路に関する
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a frequency multiplier circuit that obtains a multiplied wave of a human power wave.
従来の逓倍波を得るため、FMステレオ副搬送波再生1
.トランシーバ等に用いられている周知の周波数逓倍回
路であるP L L (Phase−Locked−L
oop ) f第1図に示す。同図において、該PLL
は内部に位相比較器1(以下、OOMPl )、低域フ
ィルタ2(以下、LPF2)、鷲圧制帥発賑器5C以下
、VOO5)、周波数分周器4(以下、D工V4)を有
する帰還系である。同図において、OOMP1は入力信
号fsとV2O3により電圧制御されDIV4によf)
fo / N (NU;i[L[)に分周された周波
数と各々位相とを比較する。そしてその出力はLPF2
’i辿って前記VOO5の制碑端子に加えられ、入力ぼ
号とVOO5の発振周波数差ならびに位相差を低減する
方向にVCIIの周波数を変化させる。この回路をルー
プさせることによ、j)fo=Nfsが得られるもので
あ56−以上、従来の周波数逓倍回路の欠点は、第一に
、構造が複雑で小型化が困難であり、しかも高価なこと
である。これはNil述のようにOOMP。To obtain the conventional multiplication wave, FM stereo subcarrier reproduction 1
.. PLL (Phase-Locked-L) is a well-known frequency multiplier circuit used in transceivers etc.
oop ) f shown in Figure 1. In the same figure, the PLL
is a feedback circuit which internally has a phase comparator 1 (hereinafter referred to as OOMPl), a low-pass filter 2 (hereinafter referred to as LPF2), a suppressor generator 5C or lower (VOO5), and a frequency divider 4 (hereinafter referred to as D-V4). It is a system. In the same figure, OOMP1 is voltage controlled by input signals fs and V2O3, and f) by DIV4.
The frequency divided into fo / N (NU; i[L[) and each phase are compared. And its output is LPF2
'i is applied to the control terminal of the VOO5, and changes the frequency of VCII in the direction of reducing the oscillation frequency difference and phase difference between the input signal and the VOO5. By looping this circuit, j) fo = Nfs can be obtained.The disadvantages of conventional frequency multiplier circuits are, firstly, that they have a complicated structure, making it difficult to miniaturize, and that they are expensive. That's true. This is OOMP as described by Nil.
LPF、VCO1D工Vといった専用の集積回路(少な
くとも、OOMPとI、PF、VOO1D工Vの3種類
)の組合せが必要であることがら、構造を複雑化するこ
と、部品コスト、実装コストが高くなること、さらに小
型化を困難にしていることなどが原因である。第二の欠
点は周波数精度が不安定なことである。これは周波?:
1梢度が精度的に限昇のあるVCOに依存しでいるころ
に原因がある。また、VCOの精度ケより向上しようと
すればさらに商価格にならぎるを得ない。It requires a combination of dedicated integrated circuits such as LPF and VCO1D (at least three types: OOMP, I, PF, and VOO1D), which complicates the structure and increases component costs and mounting costs. This is due to the fact that it is difficult to miniaturize the device. The second drawback is that frequency accuracy is unstable. Is this a frequency? :
The reason lies in the fact that the power level depends on the VCO, which has a limited accuracy. Moreover, if you try to improve the accuracy of the VCO, the commercial price will be even more prohibitive.
本発明はこのような問題点を解決“ノーるもので、その
目的とするところは、品精度な逓倍周波数の得られる安
価で小型な周波数逓倍回路を提供することにある。The present invention is intended to solve these problems, and its purpose is to provide an inexpensive and compact frequency multiplier circuit that can obtain a multiplication frequency with high precision.
入力する周波数の波形を規則的に歪ませる波形歪回路と
、該歪波形回路により規則的な歪み?有する波形を入力
波の周波数の逓倍に得7b波形整形回路とで構成するこ
と盆特徴とする周波数逓倍回路を特徴とする。A waveform distortion circuit that regularly distorts the waveform of the input frequency, and a regular distortion caused by the distorted waveform circuit? The frequency multiplier circuit is characterized in that it is configured with a 7b waveform shaping circuit that multiplies the frequency of an input wave.
本発明の冥加しIIの成り〕に入る前に本発明の背景O
こついてまず説明1−る。Background of the present invention
First of all, let me explain.
周知のように、水晶振動子等の圧電振動子r発振回路に
より共振周波数で発振させた場合、第2図(A)の波形
のような基本波(正弦波)を示す。As is well known, when a piezoelectric vibrator such as a crystal vibrator is oscillated at a resonant frequency by an oscillation circuit, it exhibits a fundamental wave (sine wave) as shown in the waveform of FIG. 2(A).
この基本波をバイアスをかけないコンプリメンタリ−回
路等の増巾器に入力させると第2図(B)のような波形
を示すことも周知である。この波形はひずみ波であり通
常は極力排除し、いかにして基本波に近ずけるかに技術
的努力が払われている。It is also well known that when this fundamental wave is inputted to an amplifier such as a complementary circuit which is not biased, a waveform as shown in FIG. 2(B) is exhibited. This waveform is a distorted wave, and technical efforts are usually made to eliminate it as much as possible and make it as close to the fundamental wave as possible.
ところが、本出願人はこのひずみ波を逆に暦月すること
により極めて容易に、シ凌)も尚硝度で安価に逓倍波を
得られることを軸めることができた。However, by reversing this distorted wave, the present applicant was able to very easily obtain a multiplied wave at low cost and at a still high nitric strength.
本発明はそのための周波数逓倍回路であり、以下実箔例
にもとすき詳細に説明する。The present invention is a frequency multiplier circuit for this purpose, and will be explained in detail below using actual foil examples.
第5図は本発明の実施例を示すブロック図であり、入力
する周波数f8の波形を規則的にひずませる波形ひずみ
回路5と、該波形ひずみ回路5によシ規則的なひずみを
有する波形を入力波の周波数f8のN倍の周波数Nfs
’((得る波形整形1i、回路6とで構成されるもので
ある。以上本例によって得られる逓倍波について第4図
の波形図にもとすいて説明する。同図(A)は第2図(
A)と同様の基本波で正弦波を示し、同図(B)はひず
み波であるが本例の説明を容易にするために第2図(B
)のひずみ波と少し、波形tSにして示しである。従来
例でも説明したように、第4図(B)に示すひずみ波は
たとえば増巾器等の過増巾により生じることは周知であ
り、本発明の波形ひずみ回路5もこれを用いている。本
例は、該波形ひずみ回路5により規則的にひずみを有す
る第4図(B)のひずみ波を波形整形回路6にょシ得ら
れる逓倍波(2〜n倍波)の−例として、同図(C)に
2倍波を、同図(D)に6倍波を各々示す。同図(0)
の2倍波を得るためには、同図(B)のP軸にしきい値
を設足し、トリガー点としてd、e、h、tおよびn%
O,r、g・・・0・を得、このトリガー点において
出力させればよい。同様にして同一(D)の6倍波を得
るためには、同図(B)のQ軸にしきい値を設ボし、ト
リガー点としてのa。FIG. 5 is a block diagram showing an embodiment of the present invention, which includes a waveform distortion circuit 5 that regularly distorts the input waveform of frequency f8, and a waveform that is regularly distorted by the waveform distortion circuit 5. Frequency Nfs that is N times the frequency f8 of the input wave
'((It is composed of the obtained waveform shaping 1i and the circuit 6. The multiplied wave obtained by this example will be explained based on the waveform diagram of FIG. 4. figure(
Figure 2 (B) shows a sine wave with the same fundamental wave as in A), and a distorted wave in Figure 2 (B) to facilitate the explanation of this example.
) is shown as a waveform tS. As explained in the conventional example, it is well known that the distorted wave shown in FIG. 4(B) is caused by excessive amplification of an amplifier, etc., and the waveform distortion circuit 5 of the present invention also uses this. In this example, the distorted wave shown in FIG. 4(B), which is regularly distorted by the waveform distortion circuit 5, is obtained by the waveform shaping circuit 6. (C) shows the second harmonic wave, and (D) shows the sixth harmonic wave. Same figure (0)
In order to obtain the second harmonic of
O, r, g...0. should be obtained and output at this trigger point. Similarly, in order to obtain the same sixth harmonic wave (D), a threshold value is set on the Q axis in (B) of the same figure, and a is set as the trigger point.
b、Qs、 f、gs jおよびに、 1、m、plq
。b, Qs, f, gs j and to, 1, m, plq
.
t・・・・・・を得、2倍波同様このトリガー点におい
て出力さぜれば良い。なお、本発明に用いる波形ひずみ
回路5は本例ではバイアスをかけないコンプリメンタリ
−回路等の増巾器にまり説明しタカ、以上の説明でも明
らかなように規則的なひずみ波が得られる波形ひずみ回
路であれば本発明の31!殉は可能である。捷だ、波形
整形回路6は波形を任意のレベルにしきいイ1ムを設尾
しトリガー点を得、出力できるものであれば本発明の実
施は可能であり、本出願人は増巾器または比牧に′Jま
たはゲート回路を用いて前述の逓倍波を得ている。々お
、本例では逓倍波として2倍、3倍波を説明したが、第
5図(B)のひずみ波を変化させることにょシ任意の逓
倍波を得ることが可能である。t... and output it at this trigger point like the second harmonic wave. In this example, the waveform distortion circuit 5 used in the present invention is an amplifier such as a complementary circuit that does not apply bias.As is clear from the above explanation, the waveform distortion circuit 5 is a waveform distortion circuit that can obtain a regular distorted wave. If it is a circuit, 31 of the present invention! Martyrdom is possible. However, the present invention can be implemented as long as the waveform shaping circuit 6 can set a threshold to set the waveform at an arbitrary level, obtain a trigger point, and output the signal. The above-mentioned multiplication wave is obtained by using 'J' or a gate circuit in Himaki. In this example, double and triple waves have been explained as the multiplied waves, but any multiplied wave can be obtained by changing the distorted wave shown in FIG. 5(B).
1、 本祐明の周波数逓倍回路は、安定な型中率を有す
る波形ひずみ回路と安定したしきい値の得られる波形整
形回路との組合せにより逓倍波の周波数の出力が得られ
るため、極めて商精度な逓倍波を提供することができる
。1. Yumei Moto's frequency multiplier circuit is extremely commercially available because it can output the frequency of the multiplied wave by combining a waveform distortion circuit with a stable model rate and a waveform shaping circuit with a stable threshold value. Accurate multiplication waves can be provided.
2、ujl形ひずみ回路と波形整形回路だけの簡易な4
ItbX、のため、集積回路で1神頬に火装できること
か、部品コスト、実装コス士を大目】に低減すZことが
可能となり小型化も実現できる。2. Simple 4 with only ujl type distortion circuit and waveform shaping circuit
Because of ItbX, it is possible to mount it in one go with an integrated circuit, and it is possible to reduce component cost and mounting cost to a large extent, and it is also possible to realize miniaturization.
第1図は従来例のブロック図。
第2図は波形図を示し、同図(A)は基本波、同図CB
)はひずみ波。
第3図は本発明の実施例を示すブロック図。
第4図(A)〜(D)は本発明の実姉例を説ヴするため
の波形図。
5は波形ひずみ回路
6は波形整形回路
以上
出願人 松島工業株式会社
矛1 図
;1=2図FIG. 1 is a block diagram of a conventional example. Figure 2 shows a waveform diagram, where (A) is the fundamental wave and CB
) is a distorted wave. FIG. 3 is a block diagram showing an embodiment of the present invention. FIGS. 4(A) to 4(D) are waveform diagrams for explaining a practical example of the present invention. 5 is a waveform distortion circuit 6 is a waveform shaping circuit Applicant: Matsushima Kogyo Co., Ltd. 1 Figure; 1 = 2 Figure
Claims (1)
回路と、該波形ひすみ回路によシ規則的なひずみ?有す
る波形を入力波の周波数の逓倍に得る波形整形回路とで
構成すること1に特徴とする周波数逓倍回路。A waveform distortion circuit that regularly distorts the waveform of the input frequency, and a regular distortion caused by the waveform distortion circuit? 1. A frequency multiplier circuit comprising: a waveform shaping circuit that obtains a waveform by multiplying the frequency of an input wave.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4635884A JPS60190018A (en) | 1984-03-09 | 1984-03-09 | Frequency multiplier circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4635884A JPS60190018A (en) | 1984-03-09 | 1984-03-09 | Frequency multiplier circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60190018A true JPS60190018A (en) | 1985-09-27 |
Family
ID=12744924
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4635884A Pending JPS60190018A (en) | 1984-03-09 | 1984-03-09 | Frequency multiplier circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60190018A (en) |
-
1984
- 1984-03-09 JP JP4635884A patent/JPS60190018A/en active Pending
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