JPS60190019A - Frequency multiplier circuit - Google Patents

Abstract

PURPOSE:To obtain a highly accurate multiple frequency with a small sized and inexpensive circuit by combining frequency multiplier circuits each comprising a waveform distortion circuit and a waveform shaping circuit in series or parallel. CONSTITUTION:The series connection between the waveform distortion circuit 5 and the waveform shaping circuit 6 is used as a basic building block. A distorted wave shown in Fig. B having a regular distortion is obtained from a fundamental wave A by the circuit 5 and a multiplied wave is obtained further by the waveform shaping circuit 6. In order to obtain, e.g., a two-multiple wave, a threshold value is set to a P axis in Fig. B and points (d), (e), (h), (i) are obtained as trigger points and an output is obtained from the points. In order to obtain a three-multiple wave, a threshold value is set to a Q axis and points (a), (b), (c), (f), (g), (j) are used as trigger points. Moreover, a high multiplication is obtained by connecting said multiplier circuits in series. Moreover, an optional frequency is obtained by the series connection of said multiplier circuit and a frequency division circuit and also a parallel circuit in Fig. A circuit 9 is a gate circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a frequency multiplier circuit that obtains a multiplied wave of an input wave.

[Prior art]

To obtain the conventional multiplication wave, FM stereo subcarrier reproduction,
PLL (Phase-Locked-LO) is a well-known same wave number multiplier circuit used in transceivers etc.
Op) is shown in FIG. In the figure, the PLL includes a phase comparator 1 (hereinafter referred to as COMPl) and a low-pass filter 2.
(hereinafter referred to as % L P F2 ), a voltage controlled oscillator 3 (hereinafter referred to as VC(1)), and a frequency divider 4 (hereinafter referred to as DIV4). Each phase is compared with the controlled frequency divided into fo/N (N is a multiplier) by DIV4.

The output thereof is applied to the control terminal of the VCO 3 through the LPF 2, and the frequency of the VC 06 is changed in the direction of reducing the oscillation frequency difference and phase difference between the input signal and the VCO 3. By looping this circuit, pfo=Nf
s is obtained.

As mentioned above, the disadvantages of the conventional frequency multiplier circuit are first that the structure is complicated, making it difficult to miniaturize, and moreover, it is expensive. As mentioned above, this is COIVf P%LPF, VCOld
Since a dedicated integrated circuit such as IV (at least a combination of COMP, LPF, and VC (J%DIV)) is required, the structure is complicated, component costs and mounting costs are high, and the size is small. The second drawback is that frequency accuracy is unstable.This is due to the fact that frequency accuracy depends on vCO, which has a limited accuracy. .Also,
If the precision of the VCO is to be further improved, the price will inevitably become even higher.

〔the purpose〕

The present invention is intended to solve these problems, and its purpose is to provide an inexpensive and compact frequency multiplication circuit that can obtain a highly accurate multiplication frequency.

〔overview〕

A frequency multiplier circuit comprising a waveform distortion circuit that regularly distorts the waveform of an input frequency, and a waveform shaping circuit that obtains a regularly distorted waveform by multiplying the frequency of the input wave by the distorted waveform circuit. A frequency multiplier circuit characterized by being combined in series or in parallel.

[Example] Before entering into the detailed description of the present invention, the background of the present invention will be explained first.

As is well known, when a piezoelectric resonator such as a crystal resonator is caused to oscillate at a resonant frequency by an oscillation circuit, it exhibits a fundamental wave (sine wave) as shown in the waveform of FIG. 2(A).

It is also well known that when this fundamental wave is inputted to an amplifier such as a complementary circuit which is not biased, a waveform as shown in FIG. 2(B) is obtained. This waveform is a distorted wave, and technical efforts are usually made to eliminate it as much as possible and make it as close to the fundamental wave as possible.

However, the present invention has been able to confirm that by inversely utilizing this distorted wave, a multiplied wave can be obtained extremely easily, with high precision, and at low cost. This will be explained in detail in the following examples.

FIG. 3 is a block diagram showing an embodiment of the present invention, which includes a waveform distortion circuit 5 that regularly distorts a waveform of an input frequency fs, and a waveform that has regular distortion by the waveform distortion circuit 5. The frequency N f which is N times the frequency f8 of
s.

The multiplied wave obtained by this example will now be explained with reference to the waveform diagram of FIG. 4.

Figure 2 (A) shows a sine wave with the same fundamental wave as Figure 2 (A), and Figure 2 (B) shows a distorted wave, but for ease of explanation of this example, Figure 2 (B) This is a slightly different waveform from the distorted wave. As explained in the conventional example, Fig. 4 (B
It is well known that the distorted waves shown in ) are caused by over-amplification, such as in an IJ amplifier.

The waveform distortion circuit 5 of the present invention also uses this.

In this example, the distorted wave shown in FIG. 4(B) which is regularly distorted by the waveform distortion circuit 5 is used as an example of a multiplied wave (2nd to nth harmonic wave) obtained by the waveform shaping circuit B. Diagram (C)
2 shows the second harmonic wave, and (D) shows the third harmonic wave. The same figure (C
), set a threshold on the P axis in the same figure (B), and use d, e, h, f and 1 as trigger points.
% o, r, a... can be obtained and output at the trigger point.

Similarly, in order to obtain the third harmonic wave shown in (D) in the same figure,
Set a threshold on the Q axis of B) and set a as the trigger point.
s bs Cs fs gs J and to, l, m.

It is sufficient to obtain p, q% L... and output it at this trigger point in the same way as the second harmonic wave. In this example, the waveform distortion circuit 5 used in the present invention has been explained using an amplifier such as a complementary circuit that does not apply bias, but as is clear from the above explanation, it is a waveform distortion circuit that can obtain regular distorted waves. If so, the present invention can be implemented. In addition, the waveform shaping circuit 6 can be used to implement the present invention as long as it can set a threshold value for the waveform at an arbitrary level, obtain a trigger point, and output the signal. Alternatively, the above-mentioned multiplied wave is obtained using a gate circuit.

In this example, the 2nd and 6th harmonic waves are used as the multiplied waves, but any multiplied wave can be obtained by changing the distorted wave shown in FIG. 5(B).

FIG. 5 shows the frequency multiplier circuit (hereinafter referred to as "the frequency multiplier circuit") explained above.

This is an embodiment in which two or more stages of multiplier circuits) 7 are connected in series,
A frequency that is multiplied by the number of stages of the multiplication amount of each of the multiplier circuits 7a to 7n can be obtained. For example, in the figure, if the first-stage multiplier circuit doubles, the second-stage multiplier circuit multiplies five times, and the third-stage multiplier circuit doubles by 1J, the human frequency fs becomes the first The output will be 2 fs at the 2nd stage, 6 fs at the 2nd stage, and 12 fs at the 6th stage, as shown in the figure.
If stages are connected, the output will be multiplied by the number of stages.

FIG. 6 shows another embodiment in which a multiplier circuit 7'' and a frequency divider circuit 8 are connected, and the input frequency is multiplied by 5 times the input frequency of the fs1 multiplier circuit 7°, and the frequency division stage of the frequency divider circuit 8 is set to 1/1. 1.5 when set to 2
・It shows the component that can obtain the fs output. By combining this configuration with FIG. 5, it is possible to select an arbitrary frequency output.

Further, FIG. 7 shows a configuration in which the embodiment of FIG. 5 and the embodiment of FIG. 6 are connected in parallel and mixed by a gate circuit 9.

〔effect〕

1. The frequency multiplier circuit of the present invention can output the frequency of the multiplied wave by combining a waveform distortion circuit with a stable amplification factor and a waveform shaping circuit with a stable threshold value, so it can produce an extremely high frequency output. Accurate multiplication waves can be provided.

2. Due to the simple configuration of only a waveform distortion circuit and a waveform shaping circuit, it can be implemented as a single type of integrated circuit, making it possible to significantly reduce component costs and mounting costs, and achieve miniaturization.

5. The frequency multiplier circuit of the present invention is capable of high frequency multiplication by series connection, and furthermore, by series connection with a conventional frequency divider and parallel connection using a gate circuit, A flexible amount of frequency multiplication can be obtained. For this reason, for example, it is easily possible to obtain temperature compensation for a microcontroller of 2 to 6 Ml (z) using a 32 KHz clock oscillator, and to obtain temperature compensation of 3-5 MHz from temperature compensation of 2 MHz. , its application range is extremely wide.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional example. Figure 2 is a waveform diagram, in which (A) shows the fundamental wave and (B)
) is a distorted wave. FIG. 6 is a block diagram showing an embodiment of the present invention. FIG. 5 is a block diagram showing one embodiment of the present invention. FIG. 6 is a block diagram showing one embodiment of the present invention. is a block diagram showing another embodiment of the present invention. 5 is a waveform distortion circuit. 6 is a waveform shaping circuit.

Claims (1)

[Claims] A frequency multiplier circuit consisting of a waveform distortion circuit that regularly distorts the waveform of the input frequency and a waveform shaping circuit that obtains a regularly distorted waveform by multiplying the frequency of the input wave by the waveform distortion circuit is connected in series or A frequency multiplier circuit characterized by being combined in parallel.