JPH01265710A - Switched capacitor type automatic variable resistor circuit - Google Patents
Switched capacitor type automatic variable resistor circuitInfo
- Publication number
- JPH01265710A JPH01265710A JP9590288A JP9590288A JPH01265710A JP H01265710 A JPH01265710 A JP H01265710A JP 9590288 A JP9590288 A JP 9590288A JP 9590288 A JP9590288 A JP 9590288A JP H01265710 A JPH01265710 A JP H01265710A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency
- switched capacitor
- variable resistor
- resistor circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 31
- 238000010586 diagram Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
Landscapes
- Filters That Use Time-Delay Elements (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はスイッチトキャパシク回路で構成されるオート
ボリウム回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an autovolume circuit composed of a switched capacitor circuit.
従来、この種のスィッチ1〜キヤパシタ型オー1〜ポリ
ウム
タの利得か入力のキャパシタと演算増幅器(以下オペア
ンプという)の帰還路のキャパシタの容量値で決定され
ることにより、入力のキャパシタの容量をスイッチで切
り替えて所望の容量比を得て、それによりフィルタの利
得を可変して所望の値にする回路が一般的であつな。Conventionally, the capacitance of the input capacitor is determined by the capacitance value of the input capacitor and the capacitor in the feedback path of the operational amplifier (hereinafter referred to as the operational amplifier). A common circuit is to obtain a desired capacitance ratio by changing the filter gain to a desired value.
上述1〜た従来のスイッチトキャパシタ型オーI〜ボリ
ウム回路は、オー1ヘポリウムの可変幅および可変数に
応じてキャパシタが必要となり、この回路をMO8型集
積回路上に集積した場合にチップザイズが大きくなると
いう欠点がある。特に、MO3型集積回路」二で集積度
が上ったとしてもスイッチは小さくなるが、キャパシタ
は比精度を上げる必要性があり、また寄生容量等の浮遊
容量が問題ならない程度の大きな容量値である必要性が
あり、才なオペアンプを構成するトランジスタもノイズ
の問題や比精度の問題があって小さくはならないという
欠点があった。The conventional switched capacitor type OI volume circuits mentioned in 1 to 1 above require capacitors depending on the variable width and variable number of the O1 heporium, and when this circuit is integrated on an MO8 type integrated circuit, the chip size becomes large. It has the disadvantage of becoming. In particular, even if the degree of integration increases with MO3 type integrated circuits, the size of the switch will become smaller, but the capacitor needs to have higher specific accuracy, and the capacitance value is large enough that stray capacitance such as parasitic capacitance is not a problem. There was a certain necessity, and the transistors that made up the sophisticated operational amplifier had the disadvantage that they could not be made smaller due to noise and ratio accuracy problems.
本発明の目的は、これらの欠点を除き、分周比により利
得を決定することにより、高精度で小さい面積に形成で
きるオートボリウム回路を提供することにある。An object of the present invention is to eliminate these drawbacks and provide an autovolume circuit that can be formed with high accuracy and in a small area by determining the gain by the frequency division ratio.
本発明の構成は、キャパシタの各電極から接続端子およ
び接地間にそれぞれスイッチを設けた回路が2つ並列に
接続されてなるスイッチ1−キャパシタ回路が演算増幅
器の入力端および入力出力端間にそれぞれ設けてなるス
イッチトキャパシタ型オートボリウム回路において、前
記2つのスイッチトキャパシタ回路の各スイッチを開閉
するクロック周波数をそれぞれ可変する可変分周手段を
備え、これら可変分周手段の分周比を可変することによ
り利得を可変することを特徴とする。The configuration of the present invention is such that two circuits each having a switch provided between each electrode of a capacitor, a connecting terminal, and ground are connected in parallel, and a switch 1 and a capacitor circuit are connected between an input terminal and an input/output terminal of an operational amplifier, respectively. The switched capacitor type autovolume circuit provided includes variable frequency dividing means for respectively varying the clock frequency for opening and closing each switch of the two switched capacitor circuits, and by varying the frequency dividing ratio of these variable frequency dividing means. It is characterized by variable gain.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)、(b)は本発明の一実施例を示す回路図
およびその波形図である。本実施例は、発振周波数fo
のオシレータ]と、この周波数foを1/M、]、/N
に分周する可変分周器2゜3と、スイッチトキャパシタ
回路4,5と、演算増幅器6とから構成され、入力端子
1.0からの信号レベルを可変して出力端子1]から出
力する。FIGS. 1(a) and 1(b) are a circuit diagram and its waveform diagram showing an embodiment of the present invention. In this embodiment, the oscillation frequency fo
oscillator] and this frequency fo is 1/M, ], /N
It is comprised of a variable frequency divider 2.3, switched capacitor circuits 4 and 5, and an operational amplifier 6, which varies the signal level from the input terminal 1.0 and outputs it from the output terminal 1.
入力側のスイッチトキャパシタ回路4のスイッチSN、
は1/N分周されたクロックφN1により開閉され、ス
イッチSN2はクロックφN2により開閉される。また
、帰還側のスイッチl−キャパシタ回路5のスイッチS
N2はクロックφ旧により開閉され、スイッチSM□は
クロックφM2により開閉される。入力側のキャパシタ
C1とキャパシタC2は同一の容量値であり、帰還側の
キャパシタC3とキャパシタC4は同一の容量値である
。switch SN of the switched capacitor circuit 4 on the input side,
is opened and closed by a clock φN1 whose frequency is divided by 1/N, and the switch SN2 is opened and closed by a clock φN2. Also, switch L on the feedback side - switch S of the capacitor circuit 5
N2 is opened and closed by clock φold, and switch SM□ is opened and closed by clock φM2. Capacitor C1 and capacitor C2 on the input side have the same capacitance value, and capacitor C3 and capacitor C4 on the feedback side have the same capacitance value.
今、Cl=C2=CR1,C3=C4=CR2とおくと
、それぞれの回路4,5は、等測的に次の抵抗値を持つ
。Now, assuming that Cl=C2=CR1, C3=C4=CR2, each circuit 4, 5 has the following resistance value isometrically.
ここで、foはオシレータ1のクロック周波数、N、M
はそれぞれの可変分周器2,3の分周数である。Here, fo is the clock frequency of oscillator 1, N, M
is the frequency division number of each variable frequency divider 2, 3.
ここで図に示すように、クロックφM1が「ハイ」でク
ロックφM2が「ロウ」のときにはスイッチSMIが閉
、スイッチSM2が開となるが、このときにはキャパシ
タC3がオペアンプの負帰還路となる。逆に、クロック
φM1が「ロウ」で、クロックφ8□が「ハイ」のとき
にはスイッチSM□が開、スイッチSM2が閉となるが
このときにはキャパシタC4がオペアンプの負帰還路と
なる。As shown in the figure, when the clock φM1 is "high" and the clock φM2 is "low", the switch SMI is closed and the switch SM2 is open, but at this time, the capacitor C3 becomes the negative feedback path of the operational amplifier. Conversely, when the clock φM1 is “low” and the clock φ8□ is “high”, the switch SM□ is open and the switch SM2 is closed, and at this time, the capacitor C4 becomes the negative feedback path of the operational amplifier.
この場合、クロックφM1とクロックφM2のずれ(ス
リット)はオペアンプ6のセットリングタイムに対して
十分短かく出来るので、オペアンプ6の入出力が同時に
切り離される時間は短かく出来、従ってオペアンプ6の
出力は飽和することなしに一定に保たれて正常動作し、
すなわち逆相増幅器の回路機能が得られる。このとき逆
相増幅器の利得は次式のようになる。In this case, the gap (slit) between the clock φM1 and the clock φM2 can be made sufficiently short with respect to the settling time of the operational amplifier 6, so the time during which the input and output of the operational amplifier 6 are simultaneously disconnected can be shortened, and therefore the output of the operational amplifier 6 is It remains constant without saturating and operates normally.
In other words, the circuit function of an anti-phase amplifier can be obtained. At this time, the gain of the anti-phase amplifier is as follows.
G=R2/R,・・(3) (1) 、 (2)式から次式か得られる。G=R2/R,...(3) From equations (1) and (2), the following equation can be obtained.
ここで、CR1/ CR2は一定値であるから、分周比
M、Nを可変すれば、利得Gが可変することになり、オ
ートボリウムで回路を構成することが出来る。Here, since CR1/CR2 are constant values, if the frequency division ratios M and N are varied, the gain G can be varied, and the circuit can be configured with an autovolume.
図からもわかるように、スイッチトキャパシタ回路の構
成を寄生容量不感型回路にしているので、(4)式で示
される利得は、それぞれの分周比M、Hの比で正確に決
まり、オートボリウムの各ステップ幅をきわめて高い精
度で得ることができる。As can be seen from the figure, since the configuration of the switched capacitor circuit is a parasitic capacitance-insensitive circuit, the gain shown by equation (4) is accurately determined by the ratio of the respective frequency division ratios M and H, and the autovolume Each step width can be obtained with extremely high accuracy.
また、MO8型集積回路上では可変分周器は容易に、し
かもオペアンプに比して小さなチップ面積て実現するこ
とが出来る。Further, on the MO8 type integrated circuit, the variable frequency divider can be easily realized with a smaller chip area than an operational amplifier.
〔発明の効果〕
以上説明したように本発明は、スイッチトキャパシタ型
増幅回路の2つの可変分周器の分周比を可変することに
より、オー)〜ボリウム回路を構成出来る効果がある。[Effects of the Invention] As explained above, the present invention has the advantage that a volume circuit can be configured by varying the frequency division ratio of two variable frequency dividers of a switched capacitor type amplifier circuit.
第1図(a)、(b)は本発明の一実施例を示す回路図
およびその波形図である。
]・・・オシレータ、2,3・・・可変分周器、4,5
・・・回路網、6・・・演算増幅器、10・・・入力端
子、1]・・・出力端子、SNI、 SN1. SMI
、 3M2・・スイッチ、CI 、C2、CB 、C4
・・・キャパシタ。FIGS. 1(a) and 1(b) are a circuit diagram and its waveform diagram showing an embodiment of the present invention. ]...Oscillator, 2, 3...Variable frequency divider, 4, 5
...Circuit network, 6...Operation amplifier, 10...Input terminal, 1]...Output terminal, SNI, SN1. SMI
, 3M2...switch, CI, C2, CB, C4
...Capacitor.
Claims (1)
ぞれスイッチを設けた回路が2つ並列に接続されてなる
スイッチトキャパシタ回路が演算増幅器の入力端および
入力出力端間にそれぞれ設けてなるスイッチトキャパシ
タ型オートボリウム回路において、前記2つのスイッチ
トキャパシタ回路の各スイッチを開閉するクロック周波
数をそれぞれ可変する可変分周手段を備え、これら可変
分周手段の分周比を可変することにより利得を可変する
ことを特徴とするスイッチトキャパシタ型オートボリウ
ム回路。A switched capacitor type autovolume in which two switched capacitor circuits each having a switch connected between each electrode of the capacitor, a connection terminal, and ground are connected in parallel between the input terminal and the input output terminal of an operational amplifier. The circuit is characterized by comprising variable frequency dividing means for respectively varying the clock frequency for opening and closing each switch of the two switched capacitor circuits, and for varying the gain by varying the dividing ratio of these variable frequency dividing means. Switched capacitor type autovolume circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9590288A JPH01265710A (en) | 1988-04-18 | 1988-04-18 | Switched capacitor type automatic variable resistor circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9590288A JPH01265710A (en) | 1988-04-18 | 1988-04-18 | Switched capacitor type automatic variable resistor circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01265710A true JPH01265710A (en) | 1989-10-23 |
Family
ID=14150226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9590288A Pending JPH01265710A (en) | 1988-04-18 | 1988-04-18 | Switched capacitor type automatic variable resistor circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01265710A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002335144A (en) * | 2001-05-08 | 2002-11-22 | Fujitsu Ltd | Circuit for switched capacitor filter |
JP5495356B2 (en) * | 2005-06-01 | 2014-05-21 | シチズンホールディングス株式会社 | Physical quantity sensor |
-
1988
- 1988-04-18 JP JP9590288A patent/JPH01265710A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002335144A (en) * | 2001-05-08 | 2002-11-22 | Fujitsu Ltd | Circuit for switched capacitor filter |
JP5495356B2 (en) * | 2005-06-01 | 2014-05-21 | シチズンホールディングス株式会社 | Physical quantity sensor |
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