JP2776725B2 - Frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer having a high frequency switching speed and a small phase noise after switching.

[0002]

2. Description of the Related Art In a conventional frequency synthesizer, a phase difference that changes every moment between a reference signal phase and a voltage-controlled oscillator phase is detected, and the phase switching is performed by performing negative feedback control on the phase signal and synchronizing the phase. I was going. The operation will be described below with reference to FIG.

The counter A11 receives a reference signal as an input and changes its value continuously.
The value is continuously changed using the output of The values of both counters correspond to the divided signal phase. Phase comparator 15
Outputs a signal proportional to the difference between the output signal phase of the counter A11 and the output signal phase of the counter B12. This signal passes through the band limiting circuit 14 and is input to the voltage controlled oscillator 15 as a control signal. The voltage controlled oscillator 15 outputs a signal based on the control signal, and this signal is
Is input to

By repeating the above operation, the phases are synchronized and the frequency is switched at the same time. The feedback loop at this time constitutes a secondary PLL related to the phase signal of the output of the voltage controlled oscillator.

In order to realize high-speed frequency acquisition with such a circuit, it is necessary to widen the band of the band limiting circuit. However, in this case, there is a problem that phase noise is deteriorated, and when used in a modulation circuit or the like, transmission characteristics are deteriorated.

On the other hand, a circuit configuration improved for the purpose of high-speed frequency switching (for example, a circuit described in the 1992 IEICE Autumn Meeting Preliminary Collection, second volume, page 255) will be described with reference to FIG. The operation of this circuit will be described below.

The numerically controlled oscillator 31 sets a value based on the channel setting and the output of the predictor 35 using the reference signal as a clock, and the counter 32 sets the value using the output of the voltage controlled oscillator 15 as an input. Value of Numerically Controlled Oscillator 31 and Counter 3
2 is compared by the phase comparator 13 and the phase comparison output is D
After being analog-converted by the A-converter 33, it is input to the voltage-controlled oscillator 15 through the band limiting circuit 14. After the pull-in, the averaging circuit 34 averages the output of the phase comparator 13, and the predictor 35 outputs the next switching frequency from the voltage control oscillator 15 according to the output of the averaging circuit 34 and the next channel instruction. The predicted value of the numerically controlled oscillator 31 that generates a control signal is output. At the time of switching the frequency, the input of the counter 32 is cut off and reset, and at the same time, the operation of the numerically controlled oscillator 31 is stopped and the predicted value is set in the numerically controlled oscillator 31 to perform frequency presetting on the band limiting circuit. . Thereafter, the operation of the numerically controlled oscillator 31 and the input of the counter 31 are started, and a normal operation of pulling in the secondary PLL is performed.

In the case of the circuit as shown in FIG. 3, if the stability of ± 2 to 3 kHz is to be obtained for a high frequency such as several GHz, the number of bits of the counter increases.
In addition, when the voltage-frequency characteristics of the voltage controlled oscillator vary, it is difficult to perform high-precision presetting.

As described above, in the conventional frequency synthesizer, it is difficult to stably realize low phase noise, high precision, and high-speed frequency switching under the condition that the voltage-frequency characteristic of the voltage controlled oscillator is allowed to vary. is there.

[0010]

Frequency synthesizer provided by the present invention as a means for solving such problems SUMMARY OF THE INVENTION, the frequency
A frequency control signal generating circuit for generating a control signal;
Adds frequency band limitation of wave number control signal,
A band limiting circuit for generating a number control signal;
Outputs a frequency signal with a frequency corresponding to the voltage of the wave number control signal
The frequency control signal.
The signal generation circuit includes a reference oscillation frequency generation section, a first counter, and a
2 counter, reset signal generation circuit, switch and mode
It consists of a switching signal generation circuit and a phase comparator.
The reference oscillation frequency generator uses a built-in crystal oscillator, etc.
Self-excitedly generates a reference frequency oscillation signal,
The counter divides the frequency of the reference frequency oscillation signal, and
The counter divides the frequency signal and generates the reset signal.
The raw circuit is longer than the slowest period of the output of the second counter.
Perform phase comparison operation in the phase comparator at a long cycle
The divided outputs of the first counter and the second counter
Generates a reset signal to reset the mode to zero
The signal generation circuit operates in frequency lock mode and phase lock mode.
Reset switch opening / closing system to control switching
Control signal, and the switch is the reset switch
When the switching control signal is in the frequency pull-in mode, the first
Sending the reset signal to the counter and the second counter.
The phase comparator operates in the frequency lock-in mode.
The output of the first counter and the output of the second counter
Receiving the output of the first counter and the output of the second counter.
Compare the frequency with the output, and based on the frequency difference between the two
Generating the frequency control signal by a voltage signal;
In the case of the phase synchronization mode, the output of the first counter and the second
Receiving the output of the second counter and the output of the first counter
The phase of the output of the second counter is compared with the output of the second counter.
Generating the frequency control signal by a voltage signal based on the difference
It is characterized by doing.

[0011]

According to the present invention, a primary loop feedback circuit having an excellent transient response speed is used. By resetting the counter once each time the phase is compared and aligning the phases of the counter, the phase difference after a certain time becomes proportional to the frequency.

By performing such an operation, a first-order loop can be formed with respect to frequency, and high-speed frequency pull-in can be performed. At this time, since the phase of the signal is not synchronized, there is a problem that the spectrum of the obtained signal is widened.However, after resetting the frequency, the reset of the counter is stopped, and the phase of the voltage-controlled oscillator output that changes every moment is referred to as the reference signal. By performing phase synchronization to follow the phase, a signal with high oscillation accuracy and high purity can be obtained.

That is, ON / O for resetting the counter
By switching between the mode in which the frequency is pulled in by the FF and the phase synchronization mode, frequency switching with high speed, high accuracy, and low phase noise can be realized at the same time.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.

FIG. 1 is a block diagram for explaining the present invention.

The counter A11 changes its value with the reference signal as input, and the counter B12 changes its value with the output of the voltage controlled oscillator 15 as input.

The phase comparator 13 outputs a signal proportional to the difference between the value of the divided output signal of the counter A11 and the value of the divided output signal phase of the counter B12, and this signal stabilizes the circuit. After passing through the band-limiting circuit 14 that operates, the signal is input to the voltage-controlled oscillator 15 as a control signal.

The voltage controlled oscillator 15 outputs a signal based on the control signal, and this signal is input to the counter B12.
This is the same operation as a normal synthesizer.

In the present invention, a mode switching signal generating circuit 16 for outputting a switching control signal for switching between a mode for rapidly pulling in a frequency and a mode for performing phase synchronization, and a switch for switching the mode based on the control signal. 17 and a reset signal generating circuit 18 for outputting a signal for controlling resetting of the counters A11 and B12 to realize the frequency pull-in mode.

For example, a circuit can be constructed using a charge pump type phase comparator as the phase comparator 13, a normal frequency dividing counter as the counters A11 and B12, and a low-pass filter or a lag-lead filter as the band limiting circuit 14.

When the frequency division number of the counter B12 is changed, the phases of the counter A11 and the counter B12 are shifted. As a result, the mode switching signal generating circuit 16 generates a signal for turning on the switch 17, and the frequency switching mode is set.

The reset signal generating circuit 18 has a counter A
A reset signal is output after ΔT when the value of 11 becomes 2π, and this resets the counters A11 and B12 via the switch 17. Assuming that the period of the reference signal is T, T + ΔT is a value longer than the slowest period of the output of the counter B. The counters A11 and B12 are reset every T + ΔT cycle. The difference between the time when the counter A11 reaches 2π and the time when the counter B12 reaches 2π is used for detecting the frequency difference between the signal input to the counter A11 and the signal input to the counter B12. for that reason,
After both the counters A11 and B12 have once reached 2π, the counters A11 and B1 will not change until either the counter A11 or the counter B12 reaches 2π.
It is necessary to set the value of ΔT to perform the reset of 2. Therefore, T + ΔT is a value longer than the latest cycle of the output of the counter B12 and the cycle of the output of the counter A11.

For example, in the case of digital cordless, the difference between the highest frequency and the lowest frequency is 3 of the lowest frequency.
%, The cycle of the reset signal (a) is set to about 1.05 times the cycle of the reference signal input to the counter A11.

The phase comparator 13 outputs a voltage proportional to the difference between the values of the counters A11 and B12. The operation of the counter A11, the counter B12 and the phase comparator 13 at this time will be described with reference to FIG.

The counters A11 and B12 are reset at time 0 to start frequency division. Counter A after T
11 outputs a frequency-divided reference pulse, and the counter B
12 outputs a pulse before and after time T according to the value of the counter. Since both counters are reset at time 0, the length of the phase comparison pulse corresponding to the time difference between the occurrence of both pulses is equal to the frequency difference at this time.

The phase comparison pulse (f) is supplied to the counter A11
When the frequency of the signal input to the counter B12 is higher than the frequency of the signal input to the counter B12, the rising edge of the output pulse (c) of the counter A rises and the positive pulse falling at the rising edge of the output pulse (e) of the counter B. Become.
Further, when the frequency of the signal input to the counter A11 is lower than the frequency of the signal input to the counter B12, the output pulse (e) of the counter B falls and rises and the output pulse (c) of the counter A rises and rises. The result is a negative pulse.

The value (g) of the control voltage increases when the phase comparison pulse (f) is positive, and decreases when the phase comparison pulse (f) is negative. Since the length of the phase comparison pulse (f) is proportional to the frequency difference between the signal input to the counter A11 and the signal input to the counter B12, the phases are not synchronized and only the frequency is pulled. At this time, the band-limiting element of the loop is only the band-limiting circuit 14. If this band-limiting circuit 14 is a low-pass filter or a lag-lead filter, this circuit forms a first-order loop with respect to the frequency. Frequency pull-in can be performed.

When the frequency difference between the signal input to the counter A11 and the signal input to the counter B12 decreases,
Alternatively, when it becomes zero, the mode switching signal generation circuit 16
Generates a signal to turn off the switch 17, and shifts to the phase synchronization mode. This operation can be easily determined by observing the phase comparison pulse (f).

When the mode shifts to the phase synchronization mode, the connection between the reset signal generation circuit 18 and the counters A11 and B12 is disconnected. Accordingly, the reset operation of the counter A11 and the counter B12 is released, and the counter A1
The difference between 1 and the divided output signal phase of the counter B12 changes continuously.

The phase comparator 13 outputs a voltage proportional to the constantly changing phase difference between the outputs of the counters A11 and B12. At this time, the counter A11 and the counter B
Operations of the phase comparator 12 and the phase comparator 13 will be described with reference to FIG.

In the phase synchronization mode, since the relative difference between the value (b) of the counter A11 and the value (d) of the counter B12 changes continuously, it starts when the value (b) of the counter A11 becomes 2π. The difference between the rising time of the output pulse (c) of the counter A11 and the rising time of the output pulse (e) of the counter B12 which rises when the value (d) of the counter B12 becomes 2π is the counter A at the comparison time.
11 is proportional to the instantaneous phase difference between the signal input to the counter 11 and the signal input to the counter B12.

The phase comparison pulse (f) is supplied to the counter A11
When the phase of the signal input to the counter B12 is earlier than the phase of the signal input to the counter B12, the rising edge of the output pulse (c) of the counter A rises and the positive pulse falling at the rising edge of the output pulse (e) of the counter B. Become.

When the phase of the signal input to the counter A11 is later than the phase of the signal input to the counter B12, the output pulse (c) of the counter A falls at the rising edge of the output pulse (e) of the counter B. It becomes a negative pulse rising at the rise.

The value (g) of the control voltage increases when the phase comparison pulse (f) is positive, and decreases when the phase comparison pulse (f) is negative. Since the length of the phase comparison pulse (f) is proportional to the instantaneous phase difference between the signal input to the counter A11 and the signal input to the counter B12, the phase is synchronized while finely adjusting the frequency. At this time, this circuit forms a secondary loop, and a stable operation and a highly accurate signal can be obtained.

As described above, the reset of the counter is turned on.
By switching between the frequency pull-in mode and the phase pull-in mode with OFF, the primary loop and the secondary loop can be switched without switching the filter.

[0036]

As described above, by switching the oscillation frequency of the voltage controlled oscillator at a high speed in the frequency pull-in mode and then shifting to the phase locked mode, the frequency accuracy and stability can be increased and the phase noise can be reduced. Becomes possible. Such a switching operation has an excellent effect that pull-in is performed without switching the loop filter and the speed of the transient response can be switched.

Further, a primary loop is formed by the reset operation of the counter, the frequency is pulled in at a high speed, and then a secondary loop is formed by canceling the reset operation to shift to the phase locked mode. , Stable operation and highly accurate signals can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a frequency synthesizer proposed in the present invention.

FIG. 2 is a configuration diagram of a conventional frequency synthesizer.

FIG. 3 is a configuration diagram of a frequency synthesizer using a phase / frequency preset.

FIG. 4 shows (a) a counter reset pulse, (b) a value of a counter A11, and (c) a counter A11 in the present embodiment.
FIG. 9 is a diagram showing an output pulse of (d), a value of a counter B12, (e) an output pulse of the counter B12, (f) a phase comparison pulse, and (g) a phase comparator output voltage.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Counter A 12 Counter B 13 Phase comparator 14 Band limiting circuit 15 Voltage controlled oscillator 16 Mode switching signal generating circuit 17 Switch 18 Reset signal generating circuit 31 Numerically controlled oscillator 32 Counter 33 DA converter 34 Averaging circuit 35 Predictor

Claims (3)

(57) [Claims] 1. A frequency control signal for generating a frequency control signal.
A generating circuit; a band limiting circuit that adds a frequency band limit of the frequency control signal to generate a band limited frequency control signal; and a voltage controlled oscillator that outputs a frequency signal having a frequency corresponding to the voltage of the band limited frequency control signal. Wherein the frequency control signal generation circuit includes a reference oscillation frequency generation unit, a first counter, a second counter, a reset signal generation circuit, a switch, a mode switching signal generation circuit, and a phase comparator. frequency generating unit generates a reference frequency oscillation signal to the self-excited using a crystal oscillator or the like which is internally provided, the first counter divides the reference frequency oscillation signal, the second counter is the frequency signal The reset signal generation circuit outputs the output of the second counter.
After performing the phase comparison operation in the phase comparator in a cycle longer than the slowest cycle, the first counter and the second
A reset signal for setting the divided output of the counter to zero is generated, and the mode switching signal generation circuit generates a frequency lock mode.
Generates a reset switch switching control signal for controlling the switching of de phase synchronous mode, the switch the reset switch-off control signal is circumferential
In the case of the wave number pull-in mode, the reset signal is sent to the first counter and the second counter. In the case of the frequency pull-in mode,
Receiving the output of the first counter and the output of the second counter;
The output of the first counter and the output of the second counter
And the frequency based on the frequency difference between the two.
The frequency control signal is generated by a signal, and the phase
In the case of the period mode, the output of the first counter and the second
The output of the first counter and the output of the
Performs phase comparison with the output of the two counters and calculates the phase difference between the two.
A frequency synthesizer for generating the frequency control signal with a voltage signal based on the frequency control signal . 2. The frequency synthesizer according to claim 1, wherein the band limiting circuit is constituted by a low-pass filter. 3. The frequency synthesizer according to claim 2, wherein said band limiting circuit is constituted by a lag-lead filter.