JPH04248715A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To attain direct phase comparison by digital signal processing by using a numeral control oscillator so as to extract a feedback phase signal by a phase component only. CONSTITUTION:An output frequency f0 of a voltage controlled oscillator 6 is subjected to 1/P division by a frequency divider 7 and a clock fCLK is outputted. Let an output of a numeral control oscillator 1 at a time 0 be phi=0. Then the NCO 1 keeps the integration of phase increment step phi for each period of an output signal fCLK of the frequency divider 7 and the output of the NCO 1 by the integration is increased stepwise by the operation of an M bit adder 101 and a register 102. Moreover, an output of a phase error correction circuit 4 is corrected for the error by the conversion of the specific conversion equation and a phase error signal epsilon is outputted after the correction.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention provides a phase-locked loop (PLL: Ph
This invention relates to an improvement of a frequency synthesizer using a locked loop) configuration.

0002

2. Description of the Related Art Conventionally, as a frequency synthesizer using a phase-locked loop (PLL) configuration capable of arbitrarily variably setting the output frequency, a voltage controlled oscillator 401 (VCO) is used as a frequency synthesizer as shown in FIG.
A feedback signal obtained by frequency-dividing the output of the oscillator (Olled Oscillator) using a variable frequency divider 402 and a reference signal with a constant frequency are input to a phase comparator 404, and the output of the phase comparator 404 is passed through a loop filter 405. VCO
401 is widely used.

0003

[Problem to be solved by the invention] In the above conventional configuration,
The phase comparator 404 is generally configured to perform multiplication processing between the reference signal and the feedback signal, and the phase error information is included in the low frequency component of the output of the phase comparator 404. Filter 405 is essential. In addition, the frequency switching time of the frequency synthesizer depends on the time constant of the loop filter 405, and in order to ensure the S/N (signal-to-noise power ratio) of the frequency synthesizer output to be above a certain value, the time constant of the loop filter 405 is dependent on the time constant of the loop filter 405. It becomes necessary to set the constant to a large value, which causes problems such as a longer frequency switching time.

An object of the present invention is to eliminate the factors that increase the circuit scale in the conventional configuration, improve the degree of freedom in setting the output frequency, and solve the problems caused by the dependence between the pitch of the set frequency and the frequency switching time. The object of the present invention is to provide a frequency synthesizer that is suitable for miniaturization and integration into an IC.

[0005]

[Means for Solving the Problems] The frequency synthesizer of the present invention integrates a phase increase step value expressed as an externally inputted digital value in accordance with the timing of an externally inputted clock. a numerically controlled oscillator that outputs a digital value modulo , as a feedback phase signal φ; a reference phase signal generation circuit that generates a sawtooth waveform reference phase signal Ψ having a value range from 0 radian to 2π radian; an adder that takes the difference Ψ-φ between the reference phase signal Ψ from the signal generation circuit and the feedback phase signal φ from the numerically controlled oscillator and outputs it as a phase error signal 1; and a phase error signal 1 from the adder. is converted according to the conversion formula number 1 (where {・}mod 2π is the remainder when divided by 2π radians), and the output range is (-π
~π) and outputs a corrected phase error signal ε; and a D/A converter that converts the corrected phase error signal ε from the phase error correction circuit into an analog value. , a voltage controlled oscillator whose output frequency is controlled by the corrected phase error signal converted into an analog value by the D/A converter;
A frequency divider that divides the frequency into P (P≧1) and supplies the frequency to the numerically controlled oscillator as the clock.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an example of the structure of a frequency synthesizer according to the present invention. In the figure, 1 is a numerically controlled oscillator (NCO).
It integrates the phase increase step value (digital value) Δφ set from the outside, and outputs the phase integrated value φ (0≦φ≦2π) as a feedback phase signal according to the timing of the externally supplied clock fCLK. Output. The circuit consists of an M-bit adder and (M
+1) bit register.

FIG. 2 is a block diagram showing an example of the configuration of the NCO 1. As shown in FIG. In the figure, reference numeral 101 denotes an M-bit adder which receives a phase increase step value Δφ set from the outside as one input, adds it to the other input, and outputs the result to a register 102, which will be described later. 102 temporarily stores the output of the M-bit adder 101, and receives a clock f supplied from the outside.
This is a (M+1) bit register that outputs at the timing of CLK. 103 is a phase correction circuit that corrects the (M+1) bit output of the register 102 so that the output range is (0 to 2π), and supplies the integrated value φ of the phase increase step value Δφ to the outside as a feedback phase signal. At the same time, it is fed back as the other input of the M-bit adder 101.

Returning to FIG. 1 again, 2 is a reference phase signal generation circuit, which generates a reference phase signal Ψ (0≦
Ψ≦2π: Ψ is a digital value) is generated and output. This circuit uses a ROM (Re) that stores a reference phase waveform in advance.
It can be easily configured by a method of periodically reading out ad OnlyMemory) or a method of using NCO. 3 is an adder, which performs an addition operation using the feedback phase signal φ from the NCO 1 as one input (subtraction value) and the reference phase signal Ψ from the reference phase signal generation circuit 2 as the other input (addition value); The result is output as the number 2 of phase error signals. 4 is the phase error signal outside 1 which is the output of adder 3
The phase error signal ε after correction according to the following conversion formula (1) Equation 3
(-π≦ε≦π) and outputs the result. However, {·}mod 2π indicates the remainder when divided by 2π radians.

[0009]

[Math 2]

[Math 3]

Reference numeral 5 denotes a D/A converter that converts the corrected phase error signal ε output from the phase error correction circuit 4, which is a digital value, into an analog value. 6 is a voltage controlled oscillator (VCO) that outputs a desired frequency using the output of the D/A converter 5 as a control signal.
Oscillator). 7 divides the frequency output from the VCO 6 to 1/P (P≧1), and
This is a frequency divider that outputs a clock fCLK that corresponds to the timing of O1.

[0011]

[Operation] The operation of the present invention based on the configuration example diagram of FIG. 1 will be explained below using the time chart of FIG. 3. The output frequency of the VCO 6 is f0, and the output frequency f0 is divided by 1/P by the frequency divider 7 to output the clock fCLK. Now, at time 0, the output of NCO1 is set to φ=0. From then on, NCO1 operates every cycle of the output signal fCLK of the frequency divider 7 (
3 (A
), it rises stepwise in steps of Δφ. Next, at time t1, when the value of φ reaches 2π or more, the operation of the phase correction circuit 103 in FIG. It rises in steps of Δφ. After time t1, the same operation as after time 0 is repeated to obtain a feedback phase signal with a sawtooth waveform. FIG. 3(B) shows the output of the reference phase signal generation circuit 2. This output is defined as the reference phase signal Ψ.

Now, consider the case in which the feedback phase signal φ is in a leading phase as shown in FIG. The number 4 of phase error signals obtained as the output of the adder 3 at this time is shown in FIG.
The waveform becomes as shown by the broken line in (C). As shown in the figure, there is a section outside the phase error signal 1 in which an error of -2π occurs every time the reference phase signal Ψ converts from 2π to 0. However, the output of the phase error correction circuit 4 corrects this error by converting the conversion equation (1), and outputs a corrected phase error signal ε as shown by the solid line in FIG. 3(C).

[0013]

[Equation 4] From the above, in the configuration according to the present invention, the reference phase signal Ψ
Since the feedback phase signal φ is direct phase information and the true phase error can be obtained in the corrected phase error signal ε, theoretically the corrected phase error signal ε does not contain any harmonic components, and the conventional It can be seen that the loop filter that was necessary for the configuration is no longer necessary. Therefore, the time constant of the loop filter, which was a factor in increasing the frequency switching time in the conventional configuration, is theoretically negligible in the present invention, so that high-speed frequency switching is possible.

The corrected phase error signal ε is sent to the D/A converter 5.
The VCO 6 is controlled so that the frequency is converted into an analog value and the desired frequency is output. The output frequency at this time further becomes the input value of the frequency divider 7 and is converted into a feedback phase signal. With this configuration of the negative feedback loop, a desired output frequency f0 can be obtained.

[0015] Here, the relationship between the output frequency f0 and the phase increase step value Δφ of the NCO1 will be derived. First, the period TR of the reference phase signal generation circuit 2, where fR is the fundamental frequency, is expressed by equation (2). Further, the period TNCO of NCO1 is given by the following equation (3).

[0020]

Since the period TR of the reference phase signal Ψ and the period TNCO of the feedback phase signal φ are the same, (2), (3)
From the equation, the following equation (4) is obtained.

[0017] Also, the timing lock fCL of NCO1
K is the following equation (5). Therefore, from equations (4) and (5), we obtain the following (6) (6
), the output frequency f0 becomes the following (
7) It can be expressed by the formula. From equation (7), it can be seen that if P and fR are constant, the output frequency f0 can be uniquely determined in a relationship that is inversely proportional to Δφ.

[0018]

[Effects of the Invention] As explained in detail above, in the frequency synthesizer configuration of the present invention, by using the NCO, it is possible to extract the feedback phase signal of only the phase component, and it is possible to directly compare the phases by digital signal processing. . Therefore,
A loop filter for removing harmonic components in the conventional configuration is no longer necessary, a signal with high frequency stability can be obtained, and the frequency pull-in time can be accelerated. Furthermore, since most of the circuits are digital signal processing, there are advantages such as miniaturization of the circuits and suitability for integration into ICs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a frequency synthesizer according to the present invention.

FIG. 2 is a diagram showing a configuration example of the NCO in FIG. 1;

FIG. 3 is a time chart of a feedback phase signal, a reference phase signal, and a phase error signal.

FIG. 4 is a block diagram of a conventional PLL-configured frequency synthesizer.

[Explanation of symbols]

1 NCO 2 Reference phase generation circuit 3 Adder 4 Phase error correction circuit 5 D/A converter 6 VCO 7 Frequency divider 101 Adder 102 Register 103 Phase correction circuit 401 VCO 402 Frequency divider 403 OSC 404 Phase comparator 405 Loop filter

Claims (1)

[Claims] Claim 1: Two phase integrated outputs obtained by integrating phase increase step values expressed as externally input digital values according to the timing of an externally input clock.
A numerically controlled oscillator that outputs a digital value modulo π radians as a feedback phase signal φ, and a reference phase signal Ψ with a sawtooth waveform having a value range from 0 radians to 2π radians.
and a reference phase signal generation circuit that generates the reference phase signal generation circuit, and calculates the difference Ψ−φ between the reference phase signal Ψ from the reference phase signal generation circuit and the feedback phase signal φ from the numerically controlled oscillator, and generates a phase error signal 1
An adder that outputs the output as
A phase error correction circuit that outputs a corrected phase error signal ε by converting it according to the remainder (remainder when divided by radian) so that the output range is (-π to π), and correction from the phase error correction circuit. a D/A converter that converts the post-phase error signal ε into an analog value; a voltage-controlled oscillator that controls an output frequency using the corrected phase error signal converted into the analog value by the D/A converter; and the voltage-controlled oscillator. A frequency synthesizer comprising: a frequency divider that divides the output frequency of an oscillator by 1/P (P≧1) and supplies the frequency to the numerically controlled oscillator as the clock. [External 1] [Math 1]