JPH09270705A - Decimal point frequency division type frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the size of an electronic device small by applying a feedback frequency signal not including a phase error generated through decimal point frequency division to a phase comparator so as to suppress the generation of spurious radiation. SOLUTION: This frequency synthesizer is provided with a phase comparator 1, an LPF 2, a VCO 3, a variable frequency divider 4, a frequency division number changeover circuit 5, a multiplier circuit 6, a counter 7, an M-bit shift register 8, and a signal selector 9. Then the selector 9 selects bits of an output signal of the shift register 8 depending on the count of the counter 7, and the output signal bits of the shift register 8 are fed to the phase comparator 1 as a feedback frequency signal. Thus, the feedback frequency signal not including a phase error generated through decimal point frequency division is fed to the phase comparator 1 so as to suppress the production of spurious radiation from the VCO 3 without the provision of an externally mounted filter or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decimal point frequency dividing type frequency synthesizer, and more particularly to phase error compensation in a decimal point frequency dividing type frequency synthesizer using a phase lock loop (PLL).

[0002]

2. Description of the Related Art FIG. 12 shows a conventional decimal point frequency dividing type frequency synthesizer. The decimal point frequency dividing type frequency synthesizer is a decimal point frequency dividing type frequency synthesizer, and includes a phase comparator (PC) 1 for detecting a phase difference between a reference frequency signal and a feedback frequency signal, and a low pass filter (LPF). 2, a voltage controlled oscillator (VCO) 3 that changes the oscillation frequency according to the input voltage, and a voltage controlled oscillator 3
It has a variable frequency divider 4 for frequency-dividing the output signal outputted by the variable frequency divider 4 to generate a feedback frequency signal, and a frequency division number switching circuit 5 for controlling the frequency division number by the variable frequency divider 4.

In this decimal point frequency dividing type frequency synthesizer, a phase comparator 1 detects a phase difference between a feedback frequency signal and a reference frequency signal, and a signal corresponding to this phase difference is input to a voltage controlled oscillator 3 through a low pass filter 2. Then
The voltage controlled oscillator 3 oscillates at a frequency according to the input signal. The signal oscillated by the voltage controlled oscillator 3 (output signal) is frequency-divided by the variable frequency divider 4 and returned to the phase comparator 1 as a feedback frequency signal to stabilize the output frequency. At this time, the setting of the frequency division number is varied on the time axis by the frequency division number switching circuit 5, so that the frequency division number is apparently expanded to the decimal point.

Here, the frequency division number of the frequency division switching circuit 5 is N, the frequency division number after the decimal point is n, the reference frequency is FR, the output frequency of the voltage controlled oscillator 3 is FO, and the feedback frequency is FV.

When the difference between the reference frequency FR and the feedback frequency FV becomes zero and the loop is completely locked, the output frequency FO is expressed by the following equation.

FO = (N + n) FR In this case, the frequency division number n below the decimal point can be expressed by the fractions in which the numerator m and the denominator M are integers.

N = m / M However, when both m and M are fixed to the integer denominator M and the decimal point is set in the numerator m, the frequency resolution is (1 / M) · FR and the output frequency FO is , (1 / M) · FR frequency steps.

[0008]

The conventional decimal point frequency dividing type frequency synthesizer is configured as described above and apparently divides the frequency below the decimal point, so that there is no phase error in the waveform of the feedback frequency signal. Has occurred.

In FIG. 13, m / M = 1/4 and N (integer)
The waveforms of the reference frequency signal (FR) and the feedback frequency signal (FV) when performing +1/4 frequency division are shown.

In the frequency division number switching circuit 5, in order to realize N + 1/4 frequency division, the frequency division number is set as one set of 4 cycles, and N, N,
It has changed to N, N + 1. Therefore, in the first to third cycles of the feedback frequency signal (FV), the reference frequency signal (F
R) causes phase errors e, 2e, and 3e.

This causes spurious in the voltage controlled oscillator 3 in the subsequent stage. Therefore, in order to maintain the accuracy of frequency synthesis, it is necessary to suppress spurious outside the semiconductor integrated circuit by using a filter or the like. Occurs. This hinders the miniaturization of electronic devices.

The present invention has been made by paying attention to the above-mentioned problems, and suppresses the spurious generation of the voltage controlled oscillator in the semiconductor integrated circuit without the need for an external filter or the like, and the phase error is suppressed. It is an object of the present invention to obtain a decimal point frequency dividing type frequency synthesizer that can be downsized while maintaining the required frequency synthesis accuracy.

[0013]

In order to achieve the above-mentioned object, a decimal point frequency dividing type frequency synthesizer according to the present invention has an integer part and a decimal part of the frequency of an output signal of a voltage controlled oscillator. A feedback frequency signal with a frequency divided by the frequency division number is generated by a variable frequency divider, the phase difference between this feedback frequency signal and the reference frequency signal is detected by a phase comparator, and a voltage-controlled oscillator is detected according to this phase difference. Controls the frequency of the output signal of, and inputs the output signal of the voltage-controlled oscillator in the decimal frequency divider type frequency synthesizer using a phase-locked loop that locks the loop when the difference between the reference frequency and the feedback frequency becomes zero. And a multiplication circuit for generating a multiplication signal obtained by multiplying this output signal by a multiplication number determined by the resolution of the part after the decimal point by the variable frequency divider, and the multiplication signal A shift register for inputting as a clock signal and delaying the output signal of the variable frequency divider by one cycle width of the multiplied signal, and a cyclical output signal of a predetermined bit of the shift register with a number according to the resolution of the decimal point. And a signal selector that selects a bit of the output signal of the shift register according to the count number of the counter and applies the shift register output signal of the selected bit to the phase comparator as a feedback frequency signal. The phase lock loop is performed by the feedback frequency signal that compensates for the phase error generated by the decimal point frequency division.

In this decimal point frequency division type frequency synthesizer, the frequency multiplication circuit generates a frequency multiplication signal by multiplying the output signal of the voltage controlled oscillator by a frequency multiplication factor determined by the resolution of the fractional part of the variable frequency divider, and the shift register generates the frequency multiplication signal. Is input as the clock signal, the output signal of the variable frequency divider is delayed by one cycle width of the multiplication signal, the signal selector selects the bit of the output signal of the shift register according to the count number of the counter, and this is selected. The shift register output signal of the selected bit is applied to the phase comparator as a feedback frequency signal. As a result, the feedback frequency signal which does not include the phase error generated by the decimal point division is given to the phase comparator, and the generation of spurious of the voltage controlled oscillator is suppressed.

According to another aspect of the present invention, there is provided a frequency division type frequency synthesizer for dividing a feedback frequency signal having a frequency obtained by dividing an integer part of a frequency of an output signal of a voltage controlled oscillator and a part after the decimal point by respective predetermined frequency division numbers. Generated by the frequency divider, the phase difference between this feedback frequency signal and the reference frequency signal is detected by the phase comparator, and the frequency of the output signal of the voltage controlled oscillator is controlled according to this phase difference. In the decimal frequency divider frequency synthesizer using a phase-locked loop that locks the loop by the difference with zero, oscillate the voltage controlled oscillator at a multiple determined by the resolution of the fractional part by the variable frequency divider, An output signal obtained by dividing this by a prescaler by a frequency division number that is the reciprocal of the multiple is applied to the variable frequency divider, A shift register for inputting a force signal as a clock signal and delaying the output signal of the variable frequency divider by one cycle width of the output signal of the voltage controlled oscillator; A counter that cyclically counts by a number according to the resolution, and a bit of the output signal of the shift register is selected according to the count number of the counter, and the phase of the shift register output signal of the selected bit is used as a feedback frequency signal. The phase lock loop is performed by using a feedback frequency signal that has a signal selector provided to a comparator and compensates for a phase error generated by decimal point frequency division.

In this decimal point frequency dividing type frequency synthesizer, the voltage controlled oscillator oscillates at a multiple determined by the resolution of the part after the decimal point by the variable frequency divider to generate a frequency signal equivalent to the above multiplied signal, and this voltage controlled oscillator is generated. The output signal of is divided by a prescaler by a division number that is the reciprocal of the multiple to obtain a normal output signal, and this is provided to the variable frequency divider, and the shift register clocks the output signal of the voltage controlled oscillator. The output signal of the variable frequency divider is delayed by one cycle width each time the input signal is input, and the signal selector selects the bit of the output signal of the shift register according to the count number of the counter. The shift register output signal of the selected bits is given to the phase comparator as a feedback frequency signal. As a result, the feedback frequency signal which does not include the phase error generated by the decimal point division is given to the phase comparator, and the generation of spurious of the voltage controlled oscillator is suppressed.

According to another aspect of the present invention, there is provided a frequency division type frequency synthesizer, in which a feedback frequency signal having a frequency obtained by dividing an integer part of a frequency of an output signal of a voltage controlled oscillator and a part after the decimal point by a predetermined frequency division number is varied. Generated by the frequency divider, the phase difference between this feedback frequency signal and the reference frequency signal is detected by the phase comparator, and the frequency of the output signal of the voltage controlled oscillator is controlled according to this phase difference. In the frequency dividing frequency synthesizer using a phase-locked loop that locks the loop when the difference between and becomes zero, a differentiator that differentiates the output signal of the voltage-controlled oscillator to output a pulse signal, and the differentiator is A delay circuit for generating a number of delay signals according to the resolution of the fractional part by the variable frequency divider by the output pulse signal; And a signal synthesizer for logically synthesizing the delayed signal, and a logical sum synthesized signal synthesized by the signal synthesizer is input as a clock signal, and the output signal of the variable frequency divider is delayed by one cycle width of the logical sum synthesized signal. A shift register, a counter for cyclically counting the output signal of a predetermined bit of the shift register with a number according to the resolution of the decimal point, and a bit of the output signal of the shift register according to the count number of the counter And a signal selector that gives the shift register output signal of the selected bit as a feedback frequency signal to the phase comparator, and a phase locked loop by the feedback frequency signal that compensates for the phase error generated by the decimal point frequency division. Is to do.

In this decimal point frequency dividing frequency synthesizer, the output signal of the voltage controlled oscillator is differentiated by the differentiator, and the delay circuit delays the number of delays by the variable frequency divider based on the differentiated signal. A signal is generated, and a signal synthesizer logically synthesizes the delayed signals to generate a logical sum synthesized signal equivalent to the above-mentioned multiplied signal. Each time the shift register inputs the logical sum combined signal as a clock signal, the output signal of the variable frequency divider is delayed by one cycle width of the logical sum combined signal, and the signal selector outputs the output signal of the shift register according to the count number of the counter. , And the shift register output signal of the selected bit is applied to the phase comparator as a feedback frequency signal. As a result, the feedback frequency signal which does not include the phase error generated by the decimal point division is given to the phase comparator, and the generation of spurious of the voltage controlled oscillator is suppressed.

A decimal point frequency dividing type frequency synthesizer according to the present invention is capable of varying a feedback frequency signal of a frequency obtained by dividing an integer part of a frequency of an output signal of a voltage controlled oscillator and a part after the decimal point by respective predetermined frequency division numbers. Generated by the frequency divider, the phase difference between this feedback frequency signal and the reference frequency signal is detected by the phase comparator, and the frequency of the output signal of the voltage controlled oscillator is controlled according to this phase difference. In the frequency dividing frequency synthesizer using a phase-locked loop that locks the loop when the difference between and becomes zero, the output signal of the voltage controlled oscillator is input, and the output signal is reduced to the decimal point by the variable frequency divider. A multiplication circuit for generating a multiplication signal multiplied by a multiplication number determined by the resolution of the section, and the output signal of the variable frequency divider to the resolution below the decimal point. A counter that cyclically counts with the same number, and the counter according to the count value of the counter each time the input signal of the multiplied signal and the output signal of the variable frequency divider is input and the output signal of the variable frequency divider is input. An enable signal generating circuit for generating an enable signal having a predetermined cycle width of a multiplied signal; and a logical product circuit for providing a logical product signal of the output signal of the variable frequency divider and the enable signal to the phase comparator as a feedback frequency signal. The phase lock loop is performed by the feedback frequency signal that compensates for the phase error generated by the decimal point frequency division.

In this decimal point frequency dividing type frequency synthesizer, the multiplier circuit generates the multiplied signal by multiplying the output signal of the voltage controlled oscillator by the multiplication factor determined by the resolution of the part after the decimal point by the variable frequency divider, and the enable signal generation circuit Each time the output signal of the variable frequency divider is input, an enable signal with a predetermined cycle width of the multiplication signal is generated according to the count value of the counter, and the AND circuit outputs the logical product of the output signal of the variable frequency divider and the enable signal. The signal is given to the phase comparator as a feedback frequency signal. As a result, the feedback frequency signal which does not include the phase error generated by the decimal point division is given to the phase comparator, and the generation of spurious of the voltage controlled oscillator is suppressed.

According to another aspect of the present invention, there is provided a frequency division type frequency synthesizer for dividing a feedback frequency signal having a frequency obtained by dividing an integer part of a frequency of an output signal of a voltage controlled oscillator and a part after the decimal point by respective predetermined frequency division numbers. Generated by the frequency divider, the phase difference between this feedback frequency signal and the reference frequency signal is detected by the phase comparator, and the frequency of the output signal of the voltage controlled oscillator is controlled according to this phase difference. In the frequency dividing point decimal frequency synthesizer using a phase-locked loop that locks the loop when the difference between and becomes zero, the output signal of the variable frequency divider is input and the output signal is reduced to the right of the decimal point by the variable frequency divider. A delay circuit for delaying in multiple stages with a number of stages determined by the resolution of the section, and the output signal of a predetermined number of stages of the delay circuit is decomposed into the part after the decimal point. A counter that cyclically counts the number of output signals of the delay circuit according to the number of counts of the counter, and the phase comparison using the output signal of the delay circuit of the selected number of stages as a feedback frequency signal. And a signal selector to be supplied to the signal processing unit, and performs a phase lock loop by a feedback frequency signal that compensates for a phase error generated by the decimal point frequency division.

In this decimal point frequency division type frequency synthesizer, the delay circuit delays the output signal of the variable frequency divider by the number of stages determined by the resolution of the part after the decimal point, and changes the number of stages of the output signal of the delay circuit according to the number of counts of the counter. The delay circuit output signal of the selected number of stages is selected and given to the phase comparator as a feedback frequency signal. As a result, the feedback frequency signal which does not include the phase error generated by the decimal point division is given to the phase comparator, and the generation of spurious of the voltage controlled oscillator is suppressed.

A decimal point frequency dividing type frequency synthesizer according to the next invention is capable of varying a feedback frequency signal of a frequency obtained by dividing the integer part of the frequency of the output signal of the voltage controlled oscillator and the part after the decimal point by respective predetermined frequency division numbers. Generated by the frequency divider, the phase difference between this feedback frequency signal and the reference frequency signal is detected by the phase comparator, and the frequency of the output signal of the voltage controlled oscillator is controlled according to this phase difference. In a frequency synthesizer using a phase-locked loop that locks the loop when the difference between and becomes zero, the variable frequency divider cyclically counts with the count value determined by the resolution of the decimal point Output of the reference frequency signal and the variable frequency divider for each count value in which the frequency signal and the output signal of the variable frequency divider have the same phase A phase lock loop including a decimal point frequency division only when the phase of the reference frequency signal and the phase of the output signal of the variable frequency divider coincide with each other. It is something to do.

In this decimal point frequency dividing type frequency synthesizer, the reference frequency signal and the output signal of the variable frequency divider are output only when the reference frequency signal and the output signal of the variable frequency divider are in phase due to the operation of the gate circuit. Input to the phase comparator,
The phase comparator operates only with a signal that has no phase error, and only when the phase of the reference frequency signal matches the phase of the output signal of the variable frequency divider, a phase-locked loop that periodically includes decimal point frequency division I do.

[0025]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the embodiments of the present invention described below, the same components as those of the above-described conventional example are denoted by the same reference numerals as those of the above-described conventional example, and description thereof will be omitted.

(First Embodiment) FIG. 1 shows a first embodiment of a decimal point frequency dividing type frequency synthesizer according to the present invention. This decimal point frequency dividing type frequency synthesizer includes a phase comparator (PC) 1, a low pass filter (LPF) 2, a voltage controlled oscillator (VCO) 3, a variable frequency divider 4, a frequency division number switching circuit 5, and a multiplication circuit. 6, a counter 7, an M-bit shift register 8, and a signal selector 9.

The multiplication circuit 6 receives the output signal (FO) of the voltage controlled oscillator 3 and multiplies the output signal (FO) by a multiplication number determined by the resolution of the fractional part of the variable frequency divider 4. appear. For example, the resolution is 1/4
In case of, it becomes 4 times.

The counter 7 cyclically counts the output signal of a predetermined bit of the shift register 8 by the number according to the resolution of the part after the decimal point, and the count value becomes phase error information. Here, the counter 7 counts up by numerator m of the fractional part n = m / M of the frequency division number at the trailing edge of the shift register output with the maximum shift register delay, and goes through 0, 1, 2, 3 Output.

The shift register 8 inputs the multiplied signal as a clock signal, and delays the output signal (FVa) of the variable frequency divider 4 by one cycle width of the multiplied signal each time the output signal of the variable frequency divider 4 is input. Let

The signal selector 9 selects a bit of the output signal of the shift register 8 according to the count number of the counter 7, and supplies the shift register output signal of the selected bit to the phase comparator 1 as a feedback frequency signal.

Next, the operation of the first embodiment will be described with reference to FIG. 2 by taking the case of the frequency division number N + 1 / M = N + 1/4 as an example.

The multiplication circuit 6 generates a multiplication signal obtained by multiplying the output signal (FO) of the voltage controlled oscillator 3 by 4 (M multiplication).
The phase error e of the frequency signal (FVa) output by the variable frequency divider 4 is the fractional part of the oscillation frequency FO (output signal) of the voltage controlled oscillator 3 and the frequency division number (frequency division ratio) of the variable frequency divider 4. It is a period width of a frequency of M times the oscillation frequency FO, and is equal to a period width of the multiplied signal, depending on the setting value of.

When the shift register 8 inputs the multiplied signal as a clock signal, the shift register 8 delays the output signal (FVa) of the variable frequency divider 4 by one cycle width of the multiplied signal, and each of the multiplied signals is delayed by one cycle. An output signal having a period width delay, a two period width delay, and a three period width delay is generated.

The signal selector 9 selects a bit of the output signal of the shift register 8 according to the count number (count output) of the counter 7, and outputs the shift register output signal of the selected bit as a feedback frequency signal (sector output) ( FV
It is given to the phase comparator 1 as b).

As a result, the feedback frequency signal FVb which does not include the phase errors e to 3e generated by the division of the decimal point is given to the phase comparator 1, and the spurious of the voltage controlled oscillator 3 is generated without the need for an external filter or the like. Is suppressed.

Further, in this case, since the phase error compensation of the feedback frequency signal is performed using the signal obtained by directly multiplying the output of the voltage controlled oscillator 3, it is possible to follow up even if the oscillation frequency of the voltage controlled oscillator 3 changes. There are advantages.

(Second Embodiment) FIG. 3 shows a second embodiment of the decimal point frequency dividing type frequency synthesizer according to the present invention. In addition, in FIG. 3, the portions corresponding to those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and the description thereof will be omitted.

In this embodiment, the voltage controlled oscillator 3
Oscillates at M times determined by the resolution of the part after the decimal point by the variable frequency divider 4, and outputs a frequency signal (VCO output signal) equivalent to the multiplied signal in the first embodiment.

A prescaler 10 is provided after the voltage controlled oscillator 3, and the prescaler 10 divides the output signal of the voltage controlled oscillator 3 by 1 / M to generate a normal output signal (FO). Output signal of prescaler 10 (F
O) is given to the variable frequency divider 4.

The shift register 8 receives the output signal of the voltage controlled oscillator 3 as a clock signal and delays the output signal (FVa) of the variable frequency divider 3 by one cycle width of the output signal of the voltage controlled oscillator 3.

Next, the operation of the second embodiment will be described by taking the case of the frequency division number N + 1 / M = N + 1/4 as an example.

The voltage controlled oscillator 3 oscillates M times, and the shift register 8 inputs the output signal of the voltage controlled oscillator 3 as a clock signal, whereby the shift register 8 outputs the output signal (FVa) of the variable frequency divider 4. The VCO output signal is delayed by one cycle width to generate output signals of the VCO output signal having one cycle width delay, two cycle width delay, and three cycle width delay, respectively.

The signal selector 9 selects a bit of the output signal of the shift register 8 according to the count number of the counter 7, and supplies the shift register output signal of the selected bit to the phase comparator 1 as the feedback frequency signal FVb.

As a result, also in this embodiment, the feedback frequency signal FVb that does not include the phase errors e to 3e generated by the decimal point frequency division is given to the phase comparator 1, and the voltage is obtained without the need for an external filter or the like. Generation of spurious of the controlled oscillator 3 is suppressed, and the same effect as in the first embodiment can be obtained.

(Third Embodiment) FIG. 4 shows a third embodiment of the decimal point frequency dividing type frequency synthesizer according to the present invention. In addition, in FIG. 4, portions corresponding to those in FIG. 1 are denoted by the same reference numerals as those in FIG.

In this embodiment, the decimal point frequency dividing type frequency synthesizer comprises a phase comparator (PC) 1, a low pass filter (LPF) 2, a voltage controlled oscillator (VCO) 3, a variable frequency divider 4 and a frequency division number switch. In addition to the circuit 5, a counter 7
An M-bit shift register 8, a signal selector 9, a differentiator 11, a delay element 12, and a signal combiner O.
It has an R element 13.

The differentiator 11 differentiates the output signal (FO) of the voltage controlled oscillator 3 and outputs a pulse signal. The delay element 12 generates the number of delay signals according to the resolution of the part after the decimal point by the variable frequency divider 4 by the differential signal output from the differentiator 11.

The OR element (signal combiner) 13 logically sums the delayed signals output from the delay element 12 to generate a signal equivalent to the multiplied signal in the first embodiment.

The shift register 8 receives the logical sum synthesized signal synthesized by the OR element 13 as a clock signal, and delays the output signal (FVa) of the variable frequency divider 4 by one cycle width of the logical sum synthesized signal.

The counter 7 and the signal selector 9 are the same as those in the first embodiment.

Next, the operation of the third embodiment will be described by taking the case of the frequency division number N + 1 / M = N + 1/4 as an example.

FIG. 5 shows a timing chart in OR combination. The differentiator 11 differentiates the output signal (FO) of the voltage controlled oscillator 3 to generate the pulse signal SO. This pulse signal SO is delayed by the delay element 12 to generate a number of delayed signals (SDa, SDb, SDc) according to the resolution of the part after the decimal point by the variable frequency divider 4. By OR-combining the output signal SO of the differentiator 11 and the output signals (SDa, SDb, SDc) of the delay element 12 by the OR element 13, it is possible to generate a pulse signal that is an integral multiple of FO. A logical sum combined signal equivalent to a multiplied signal of 1 is obtained.

When the shift register 8 inputs the logical product composite signal as a clock signal, the shift register 8
The output signal (FVa) of the variable frequency divider 4 is delayed by one cycle width of the logical product composite signal to generate output signals of one cycle width delay, two cycle width delay, and three cycle width delay, respectively. .

In this case as well, the signal selector 9 causes the counter 7 to operate.
The bit of the output signal of the shift register 8 is selected according to the count number of 1 and the shift register output signal of the selected bit is given to the phase comparator 1 as the feedback frequency signal FVb.

As a result, also in this embodiment, the feedback frequency signal FVb that does not include the phase errors e to 3e generated by the decimal point frequency division is given to the phase comparator 1, and the voltage is obtained without the need for an external filter or the like. Generation of spurious of the controlled oscillator 3 is suppressed, and the same effect as in the first embodiment can be obtained.

(Embodiment 4) FIG. 6 shows an embodiment 4 of the frequency dividing decimal point frequency synthesizer according to the present invention. Note that, in FIG. 6, the portions corresponding to those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and the description thereof will be omitted.

In this embodiment, a decimal point frequency dividing type frequency synthesizer comprises a phase comparator (PC) 1, a low pass filter (LPF) 2, a voltage controlled oscillator (VCO) 3, a variable frequency divider 4 and a frequency division number switch. In addition to the circuit 5, a multiplication circuit 6 and
It has a counter 7, an enable signal generation circuit 14, and an AND element 15 which is a logical product circuit.

The multiplying circuit 6 is the same as that in the first embodiment, inputs the output signal (FO) of the voltage controlled oscillator 3, and outputs the output signal (FO) to the resolution below the decimal point by the variable frequency divider 4. Generates a multiplied signal multiplied by a multiplication number determined by.

The counter 7 outputs the output signal (F
Va) is cyclically counted with the number according to the resolution of the part after the decimal point.

The enable signal generation circuit 14 inputs the multiplication signal and the output signal (FVa) of the variable frequency divider 4, and the count value of the counter 7 is input each time the output signal (FVa) of the variable frequency divider 4 is input. An enable signal having a predetermined cycle width of the multiplied signal is generated.

The AND element 15 gives a logical product signal of the output signal (FVa) of the variable frequency divider 4 and the enable signal to the phase comparator 1 as a feedback frequency signal.

Next, the operation of the fourth embodiment will be described with reference to FIG. 7 by taking the case of the frequency division number N + 1 / M = N + 1/4 as an example.

The multiplication circuit 6 generates a multiplication signal obtained by multiplying the output signal (FO) of the voltage controlled oscillator 3 by 4 (M multiplication).

The enable signal generation circuit 14 generates an enable signal having a predetermined cycle width of the multiplication signal according to the count value of the counter 7 each time the output signal (FVa) of the variable frequency divider 4 is input. In this case, the enable signal becomes a signal having one cycle width, two cycle widths, and three cycle widths of the multiplied signal according to the counter outputs 1, 2, and 3.

The enable signal is input to the AND element 15, and the AND element 15 takes a logical product of the enable signal and the output signal (FVa) of the variable frequency divider 4 to output a high level signal (logical product signal) as a feedback frequency signal. It is given to the phase comparator 1 as (FVb).

As a result, the output signal of the variable frequency divider 4 (FV
It becomes as if a) is masked by the enable signal, and the feedback frequency signal (FVb) that does not include the phase error generated by the decimal point frequency division is given to the phase comparator 1, and an external filter or the like is required. Therefore, generation of spurious of the voltage controlled oscillator 1 is suppressed.

The output signal (FVa) of the variable frequency divider 4
Since the mask is applied by the enable signal, the pulse width of the feedback frequency signal (FVb) is narrowed,
Since the phase comparator 1 performs the phase comparison with the rising edge of two inputs, no inconvenience occurs.

(Fifth Embodiment) FIGS. 8 and 9 show a fifth embodiment of the decimal point frequency dividing type frequency synthesizer according to the present invention. 8 and 9, the parts corresponding to those in FIG. 1 are designated by the same reference numerals as those in FIG. 1 and their description is omitted.

In this embodiment, the decimal point frequency dividing type frequency synthesizer includes a phase comparator 1, a low pass filter 2, a voltage controlled oscillator 3, a variable frequency divider 4, a frequency division number switching circuit 5, and a counter 7. , A signal selector 9 and a delay circuit 16.

The counter 7 cyclically counts a predetermined number of output signals of the delay circuit 16 with a number corresponding to the resolution of the decimal point.

The signal selector 9 selects the number of stages of the output signal of the delay circuit 16 according to the count number of the counter 7,
The output signal of the selected number of stages is fed back to the feedback frequency signal (FV
It is given to the phase comparator 1 as b).

The delay circuit 16 receives the output signal (FVa) of the variable frequency divider 4 and delays this output signal (FVa) by the number of stages determined by the resolution of the fractional part of the variable frequency divider 4.

FIG. 9 shows a concrete example of the delay circuit 16. The delay circuits 16 are arranged in series with each other.
Each of the delay elements 16a, 16b, 16c is provided with signal output terminals 17a to 17d for extracting a signal from the front stage of the first stage delay element 16a and the rear stage of each stage delay element 16a, 16b, 16c. ing. Each of the delay elements 16a, 16b, and 16c delays one cycle of a frequency that is M times the intermediate oscillation frequency of the voltage controlled oscillator 3, here, four times the frequency, here.

As a result, the count number of the counter 7 is 0,
The signal output terminals 17a to 17d are sequentially selected by the signal selector 9 in accordance with 1, 2, and 3, so that the feedback frequency signal (FV
b) is a frequency signal that does not include a phase error.

As a result, the feedback frequency signal (FVb) which does not include the phase error generated by the decimal point frequency division is given to the phase comparator 1, and the spurious of the voltage controlled oscillator 3 is generated without the need for an external filter or the like. Suppressed.

This embodiment is effective when the oscillation frequency range of the voltage controlled oscillator 3 is extremely lower than the oscillation frequency and does not require the multiplication circuit 6, so that the circuit configuration can be further downsized.

(Sixth Embodiment) FIG. 10 shows a sixth embodiment of the decimal point frequency dividing type frequency synthesizer according to the present invention. In addition, in FIG. 10, the portions corresponding to those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and the description thereof will be omitted.

In this embodiment, a gate circuit 18 which selectively allows passage to the input portion of the reference frequency signal (FRa) to the phase comparator 1 and the input portion of the output signal (FVa) of the variable frequency divider 4, 19 are provided.

As shown in FIG. 11, gate circuits 18 and 1
9 cyclically counts the count value determined by the resolution of the fractional part by the variable frequency divider 4, in other words, inputs the count value of the counter 7 (phase error information), and changes it with the reference frequency signal (FRa). For each count value in which the output signal (FVa) of the frequency divider 4 has the same phase, the reference frequency signal (FRc) and the output signal (FVa of the variable frequency divider 4
c) is input to the phase comparator 1.

In this embodiment, the reference frequency signal (F
Only when Ra) and the output signal (FVa) of the variable frequency divider 4 are in phase, the gate circuits 18 and 19 phase the reference frequency signal (FRc) and the output signal (FVc) of the variable frequency divider 4. Input to the comparator 1. As a result, the phase comparator 1 operates only with a signal in which no phase error has occurred, and a cycle is generated only when the phase of the reference frequency signal (FRa) matches the phase of the output signal (FVa) of the variable frequency divider 4. Therefore, a phase-locked loop including decimal point division is performed, and spurious of the voltage controlled oscillator 3 is suppressed without requiring an external filter or the like.

[0081]

As can be understood from the above description, the decimal point frequency dividing frequency synthesizer according to the present invention is
The shift register inputs the multiplied signal as a clock signal to delay the output signal of the variable frequency divider by one cycle width of the multiplied signal, and the shift register output signal of the bit selected by the signal selector according to the count number of the counter Is fed to the phase comparator as a feedback frequency signal, the feedback frequency signal that does not include the phase error generated by the decimal point frequency division is fed to the phase comparator, so that the semiconductor integrated circuit does not require an external filter or the like. Thus, the generation of spurious of the voltage controlled oscillator is suppressed, the required frequency synthesis accuracy without phase error is maintained, and the electronic device can be downsized. If a filter for suppressing spurious is used externally, it is possible to obtain a filter having the same size as the conventional one and higher accuracy.

In the decimal point frequency dividing type frequency synthesizer according to the next invention, every time the shift register inputs the output signal of the voltage controlled oscillator equivalent to the multiplication signal as the clock signal, the output signal of the variable frequency divider is supplied to the voltage controlled oscillator. The output signal of is delayed by one cycle width and the shift register output signal of the bit selected by the signal selector is given to the phase comparator as the feedback frequency signal, so the feedback frequency signal that does not include the phase error generated by the decimal point division is Since it will be given to the phase comparator, spurious of the voltage controlled oscillator will be suppressed in the semiconductor integrated circuit without the need for an external filter, etc. Can be downsized.

In the decimal point frequency dividing type frequency synthesizer according to the next invention, the output signal of the variable frequency divider is delayed by one cycle width of the logical sum synthesized signal each time the shift register inputs the logical sum synthesized signal as the clock signal. , Since the shift register output signal of the bit selected by the signal selector according to the count number of the counter is given to the phase comparator as the feedback frequency signal, the feedback frequency signal that does not include the phase error generated by the decimal point frequency division is the phase comparator. Therefore, the spurious generation of the voltage controlled oscillator is suppressed in the semiconductor integrated circuit without the need for an external filter, etc., and the required frequency synthesis accuracy with no phase error is maintained and the electronic device is downsized. it can.

In the decimal point frequency dividing type frequency synthesizer according to the next invention, every time the enable signal generating circuit inputs the output signal of the variable frequency divider, the enable signal for a predetermined period of the multiplication signal corresponding to the count value of the counter is generated. Is generated and the logical product signal of the output signal of the variable frequency divider and the enable signal is given to the phase comparator as the feedback frequency signal, so the feedback frequency signal that does not include the phase error generated by the decimal point frequency division Since it will be given to the comparator, the spurious of the voltage controlled oscillator is suppressed in the semiconductor integrated circuit without the need for an external filter and the like, and the required frequency synthesis accuracy with no phase error can be maintained and the electronic device can be maintained. Can be miniaturized.

In the decimal point frequency dividing type frequency synthesizer according to the next invention, the delay circuit delays the output signal of the variable frequency divider by the number of stages determined by the resolution of the part after the decimal point, and outputs the output of the delay circuit according to the count number of the counter. Since the number of signal stages is selected and the delay circuit output signal of the selected number of stages is given to the phase comparator as the feedback frequency signal, the feedback frequency signal that does not include the phase error generated by the decimal point division is given to the phase comparator. Therefore, the generation of spurious of the voltage controlled oscillator is suppressed in the semiconductor integrated circuit without the need for an external filter, and the required frequency synthesis accuracy without phase error can be maintained and the electronic device can be downsized.

In the decimal point frequency dividing type frequency synthesizer according to the next invention, the operation of the gate circuit causes the reference frequency signal and the variable frequency divider to be in phase only when the reference frequency signal and the output signal of the variable frequency divider have the same phase. The output signal of is input to the phase comparator, the phase comparator operates only by the signal that has no phase error, and only when the phase of the reference frequency signal and the phase of the output signal of the variable frequency divider match. Since the phase lock loop including the decimal point frequency division is periodically performed, the spurious generation of the voltage controlled oscillator is suppressed in the semiconductor integrated circuit without the need for an external filter or the like, and the electronic device can be downsized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a decimal point frequency dividing type frequency synthesizer according to the present invention.

FIG. 2 is a timing chart showing the waveform of each signal in the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of a decimal point frequency dividing type frequency synthesizer according to the present invention.

FIG. 4 is a block diagram showing a third embodiment of a decimal point frequency dividing type frequency synthesizer according to the present invention.

FIG. 5 is a timing chart showing OR combination according to the third embodiment.

FIG. 6 is a block diagram showing a fourth embodiment of a decimal point frequency dividing type frequency synthesizer according to the present invention.

FIG. 7 is a timing chart showing waveforms of respective signals in the fourth embodiment.

FIG. 8 is a block diagram showing a fifth embodiment of a decimal point frequency dividing type frequency synthesizer according to the present invention.

FIG. 9 is a block diagram showing a specific example of a delay circuit used in the fifth embodiment.

FIG. 10 is a block diagram showing a sixth embodiment of a decimal point frequency dividing type frequency synthesizer according to the present invention.

FIG. 11 is a timing chart showing a waveform of each signal in the sixth embodiment.

FIG. 12 is a block diagram showing a conventional decimal point frequency dividing type frequency synthesizer.

FIG. 13 is a timing chart showing the waveform of each signal in the conventional decimal point frequency dividing type frequency synthesizer.

[Explanation of symbols]

1 phase comparator, 2 low pass filter, 3 voltage controlled oscillator, 4 variable frequency divider, 5 frequency division number switching circuit, 6 multiplication circuit, 7 counter, 8 shift register, 9 signal selector, 10 prescaler, 11 differentiator, 12
Delay element, 13 OR element, 14 enable signal generation circuit, 15 AND element, 16 delay circuit, 1
8, 19 Gate circuit

Claims (6)

[Claims] 1. A variable frequency divider generates a feedback frequency signal having a frequency obtained by dividing an integer part and a part after the decimal point of a frequency of an output signal of a voltage controlled oscillator by respective predetermined frequency division numbers,
The phase difference between this feedback frequency signal and the reference frequency signal is detected by the phase comparator, the frequency of the output signal of the voltage controlled oscillator is controlled according to this phase difference, and the difference between the reference frequency and the feedback frequency becomes zero. In the frequency synthesizer using a phase-divided decimal point that locks the loop, the output signal of the voltage-controlled oscillator is input, and the output signal is multiplied by the resolution of the fractional part of the variable frequency divider. A shift circuit for generating a multiplied signal multiplied by, a shift register for inputting the multiplied signal as a clock signal, and delaying the output signal of the variable frequency divider by one cycle width of the multiplied signal; A counter that cyclically counts the number of bit output signals according to the resolution below the decimal point; A signal selector for selecting a bit of the shift register output signal according to the count number of the shift register, and providing the shift register output signal of the selected bit as a feedback frequency signal to the phase comparator. Phase-division frequency synthesizer characterized by performing a phase-locked loop with a feedback frequency signal that compensates for the phase error generated by. 2. A variable frequency divider generates a feedback frequency signal having a frequency obtained by dividing the integer part and the decimal part of the frequency of the output signal of the voltage controlled oscillator by a predetermined frequency division number.
The phase difference between this feedback frequency signal and the reference frequency signal is detected by the phase comparator, the frequency of the output signal of the voltage controlled oscillator is controlled according to this phase difference, and the difference between the reference frequency and the feedback frequency becomes zero. In the frequency division frequency synthesizer using a phase-locked loop that locks the loop, the voltage-controlled oscillator is oscillated at a multiple determined by the resolution of the fractional part of the variable frequency divider, and this is multiplied by the prescaler. An output signal divided by an inverse frequency division number is given to the variable frequency divider, an output signal of the voltage controlled oscillator is input as a clock signal, and an output signal of the variable frequency divider is output from the voltage controlled oscillator. A shift register for delaying the signal by one cycle width; A counter that cyclically counts by a number according to, and a bit of the output signal of the shift register is selected according to the count number of the counter, and the shift register output signal of the selected bit is used as the feedback frequency signal for the phase. A phase-divided frequency synthesizer having a signal selector provided to a comparator and performing a phase-locked loop with a feedback frequency signal that compensates for a phase error caused by frequency division. 3. A variable frequency divider generates a feedback frequency signal having a frequency obtained by dividing the integer part and the fractional part of the frequency of the output signal of the voltage controlled oscillator by each predetermined frequency division number,
The phase difference between this feedback frequency signal and the reference frequency signal is detected by the phase comparator, the frequency of the output signal of the voltage controlled oscillator is controlled according to this phase difference, and the difference between the reference frequency and the feedback frequency becomes zero. In a frequency divider with decimal point division using a phase-locked loop that locks the loop, a differentiator that differentiates the output signal of the voltage-controlled oscillator to output a pulse signal, and the pulse signal output by the differentiator causes the variable A delay circuit that generates a number of delay signals according to the resolution of the fractional part by a frequency divider, a signal synthesizer that performs a logical sum synthesis of the delay signals of the delay circuit, and a logical sum synthesis that is synthesized by the signal synthesizer A shift register for inputting a signal as a clock signal and delaying the output signal of the variable frequency divider by one cycle width of the logical sum combined signal. A counter that cyclically counts the output signal of a predetermined bit of the shift register with a number according to the resolution of the decimal point, and a bit of the output signal of the shift register according to the count number of the counter. And a signal selector that supplies the selected bit shift register output signal to the phase comparator as a feedback frequency signal, and performs a phase lock loop with the feedback frequency signal that compensates for the phase error caused by the decimal point division. A decimal point frequency dividing type frequency synthesizer. 4. A variable frequency divider generates a feedback frequency signal having a frequency obtained by dividing an integer part and a part after the decimal point of the frequency of the output signal of the voltage controlled oscillator by respective predetermined frequency division numbers,
The phase difference between this feedback frequency signal and the reference frequency signal is detected by the phase comparator, the frequency of the output signal of the voltage controlled oscillator is controlled according to this phase difference, and the difference between the reference frequency and the feedback frequency becomes zero. In the frequency synthesizer using a phase-divided decimal point that locks the loop, the output signal of the voltage-controlled oscillator is input, and the output signal is multiplied by the resolution of the fractional part of the variable frequency divider. A multiplying circuit that generates a multiplied signal multiplied by, a counter that cyclically counts the output signal of the variable frequency divider with a number according to the resolution of the fractional part, and the multiplying signal and the variable frequency divider. Input the output signal and
An enable signal generation circuit that generates an enable signal having a predetermined cycle width of the multiplied signal according to the count value of the counter each time the output signal of the variable frequency divider is input; an output signal of the variable frequency divider; And a logical product circuit for giving a logical product signal of the enable signal as a feedback frequency signal to the phase comparator, and performing a phase lock loop by a feedback frequency signal that compensates for a phase error generated by decimal point division. Decimal point frequency dividing frequency synthesizer. 5. A variable frequency divider generates a feedback frequency signal having a frequency obtained by dividing the integer part and the fractional part of the frequency of the output signal of the voltage controlled oscillator by respective predetermined frequency division numbers,
The phase difference between this feedback frequency signal and the reference frequency signal is detected by the phase comparator, the frequency of the output signal of the voltage controlled oscillator is controlled according to this phase difference, and the difference between the reference frequency and the feedback frequency becomes zero. In the frequency synthesizer with a decimal point divider using a phase-locked loop that locks the loop, the output signal of the variable frequency divider is input, and the number of stages determined by the resolution of the fractional part of the output signal of the variable frequency divider is input. A delay circuit for delaying in multiple stages, a counter for cyclically counting the output signals of a predetermined number of stages of the delay circuit with a number according to the resolution of the decimal point, and a delay circuit for the delay circuit according to the count number of the counter. The number of stages of the output signal is selected, and the delay circuit output signal of the selected number of stages is used as the feedback frequency signal. And a signal selector for providing the phase comparator, fractional-frequency type frequency synthesizer and performs phase-locked loop by feedback frequency signal to compensate for phase error produced by fractional-division. 6. A variable frequency divider generates a feedback frequency signal having a frequency obtained by dividing an integer part and a part after the decimal point of the frequency of the output signal of the voltage controlled oscillator by respective predetermined frequency division numbers,
The phase difference between this feedback frequency signal and the reference frequency signal is detected by the phase comparator, the frequency of the output signal of the voltage controlled oscillator is controlled according to this phase difference, and the difference between the reference frequency and the feedback frequency becomes zero. In the frequency synthesizer using a phase-locked loop in which the loop is locked, the number is cyclically counted with a count value determined by the resolution of the fractional part of the variable frequency divider, and the reference frequency signal and the variable frequency The output signal of the frequency divider has a gate circuit that allows the reference frequency signal and the output signal of the variable frequency divider to be input to the phase comparator for each count value, and the phase of the reference frequency signal It is characterized in that a phase-locked loop including decimal point division is periodically performed only when the phase of the output signal of the variable frequency divider matches. Several points dividing type frequency synthesizer.