JPH0923155A - Digital pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce phase jitter by including a noise shaver in a 1st loop and controlling a digital variable frequency signal generating means by a comparison output from a digital phase comparing means through the noise shaver. SOLUTION: A feedback counter 3 divides the frequency of an output clock formed by an analog VCO 10 into 1/n and outputs frequency-divided data to a digital phase comparator 4. The comparator 4 compares the phase of a reference input signal with that of the output clock supplied through the counter 3 and outputs phase error data to be a comparison data to the noise shaver 6 through a digital loop filter 5. The shaver 6 converts the plane quantized noise spectrum of the phase error data into a high frequency up spectrum. When the high frequency is suppressed by an analog loop filter 9 in an inner loop, phase jitter generated in an oscillation output, i.e., an output clock, from the VCO 10 can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual loop digital PLL circuit.

[0002]

2. Description of the Related Art Conventionally, as means for obtaining an output signal having a frequency n times as high as that of an input signal and being phase-locked to the input signal, an n divided signal obtained by dividing the output signal by n is used. A PLL circuit is known in which phase comparison is performed with an input signal by a phase comparison means, and the oscillation phase of an oscillation means for generating the output signal is feedback-controlled by a phase difference signal obtained as a comparison output of the phase comparison means. There is. Then, the voltage controlled oscillator (VC
O) The analog PLL that controls the oscillation frequency
A digital PLL circuit in which a part of or the whole of an analog PLL circuit is formed by a digital circuit is practically used.

For example, in a digital video signal processing circuit for processing an HDTV system video signal, a PLL circuit is used to form a clock having a frequency n times that of the input horizontal synchronizing pulse from the horizontal synchronizing pulse of the input video signal. To be

FIG. 13 shows the horizontal sync pulse n
It is an example of a conventional digital PLL circuit that forms a double clock. In FIG. 13, for example, a horizontal synchronizing pulse f _{H of} an HDTV video signal is input to the input terminal 51.
Is supplied. The horizontal synchronizing pulse f _H of the HDTV video signal is a positive / negative symmetrical three-valued pulse. This horizontal synchronizing pulse f _H is supplied from the input terminal 51 to the A / D converter 52. The master clock MCK is supplied to the A / D converter 52. A / D converter 52
The horizontal synchronizing pulse f _H input at is digitized.

The output of the A / D converter 52 is supplied to the digital phase comparator 53. The output of the analog VCO 54 is supplied to the digital phase comparator 53 via the n frequency divider 55. The digital phase comparator 53 is, for example, an A / D
The digital horizontal synchronizing pulse f _H from the converter 52 is
It is composed of a sampling circuit that performs sampling at the timing when a pulse is output from the n frequency divider 55. HDT
Since the horizontal synchronizing pulse f _H of the V system video signal is a positive / negative symmetrical three-valued pulse, phase comparison data between the phase of the output pulse of the n frequency divider 55 and the phase of the input horizontal synchronizing pulse is formed. .

That is, the digital phase comparator 53 comprises a flip-flop 61 as shown in FIG. 14, for example. A is input to the data input terminal of the flip-flop 61.
The output of the / D converter 52 is supplied. The output of the n frequency divider 55 is supplied to the enable terminal of the flip-flop 61. The master clock MCK is supplied to the clock input terminal of the flip-flop 61. The output of the flip-flop 61 is output via the inverter 62.

A three-valued horizontal synchronizing pulse f _H is supplied to the input terminal 51, and a digital horizontal synchronizing pulse as shown in FIG. 15A is supplied to one input end of the digital phase comparator 53. On the other hand, the analog VCO 54 outputs a clock as shown in FIG.
From, a 1 / n clock is output, as shown in FIG. 15B. The digital horizontal synchronizing pulse is sampled at the rising edge of the output of the n frequency divider 55, for example. Since the horizontal synchronizing pulse f _H is a positive / negative symmetrical three-valued pulse, it forms phase comparison data between the phase of the output pulse of the n frequency divider 55 and the phase of the input horizontal synchronizing pulse, as shown in FIG. 15D. .

In FIG. 13, the digital phase comparator 53
Is supplied to the D / A converter 57 via the digital loop filter 56. Digital loop filter 5
6 and the D / A converter 57 have a master clock MCK.
Is supplied. The D / A converter 57 converts the phase error data into an analog signal voltage. The output of this D / A converter 57 is supplied to the analog VCO 54, and D / A
The oscillation frequency of the analog VCO 54 is controlled according to the output of the A converter 57.

The output of the analog VCO 54 is output from the output terminal 5.
It is output from 9 and supplied to the digital phase comparator 53 via the n frequency divider 55. Thus, the phase locked loop is formed, from the output terminal 59, n times the clock signal nf _H of the input horizontal sync pulses f _H is obtained.

However, in the above-mentioned conventional PLL circuit,
The stability is not good because the analog VCO 54 is used. Therefore, as shown in FIG.
A configuration using a digital VCO 74 instead of 54,
The output data of the digital loop filter 56 is digital V
It can be considered that the oscillation frequency of the CO 74 is controlled. That is, the output of the digital loop filter 56 is supplied to the digital VCO 74. Digital VCO74
Is supplied to the D / A converter 75. The output of the D / A converter 75 is output via the multiplication circuit 76 to the output terminal 7
7 and the digital phase comparator 53 through the n frequency divider 55.

The digital VCO 74 can be constructed, for example, as shown in FIG. In FIG. 17, the input terminal 81
The error data D _e is supplied. Carrier wave data D _f is supplied to the input terminal 82. In the adder 82, the error data _De and the carrier wave data _Df are added. The output of the adder 82 is supplied to the adder 83. The output of the adder 83 is supplied to the modulo arithmetic circuit 84. The output of the modulo arithmetic circuit 84 is supplied to the latch 85. Latch 8
A fixed clock ACK is supplied to 5. Latch 8
5 is supplied to the adder 83, and the ROM 8
6 addresses. Waveform data is stored in the ROM 86. The output of the ROM 86 is taken out from the output terminal 88.

An accumulator circuit is formed by the adder 83 and the latch 85, and the address of the ROM 86 is incremented by the fixed clock ACK in this accumulator circuit. The number of increments in the value of the ROM 86 is set according to the output data of the adder 82. The modulo arithmetic circuit 84 has RO
It corresponds to the number of addresses of M86, and when the address is stepped up to a predetermined number, the address is returned to the start position by the modulo arithmetic circuit 84. When the error data D _e applied to the input terminal 81 is increased, the number of stepping of the address is increased, since the address is advanced rapidly, the oscillation frequency increases. When the error data D _e is small, the smaller the number of stepping of the address, since the address is advanced slowly, the oscillation frequency decreases.

The address generator for the ROM is
If modulo 2 is taken, a predetermined waveform can be obtained by directly outputting the output of this address generator or outputting only the MSB without using a ROM.

[0014]

By the way, the analog P
In the LL circuit, due to the sampling theorem, the band frequency of the feedback loop must be lower than the frequency of the reference input signal that is phase-compared with the frequency-divided signal obtained by frequency-dividing the output signal by the frequency-dividing means. However, since noise of a frequency component higher than the band frequency of the feedback loop cannot be suppressed, there is a problem that it is easily affected by noise.

Further, in the digital PLL circuit having the above-mentioned structure, since a multi-bit D / A converter is required as the D / A converters 57 and 75, the circuit structure must be complicated and expensive. There is a problem. Further, a fixed clock ACK is required to operate the digital VCO 74. Therefore, as shown in FIG. 16, when the digital VCO 74 is used as the VCO, a circuit portion 91 that operates by the master clock MCK and a circuit portion 91 that operates by the fixed clock ACK are generated. In this way, if there are circuit portions that are driven by fixed clocks that are unrelated to each other, it becomes difficult to form an integrated circuit.

Therefore, an object of the present invention is that the structure is simple and does not require a plurality of fixed clocks independent of each other.
Moreover, it is to provide a digital PLL circuit whose operation is stable.

[0017]

A digital P according to the present invention
The LL circuit compares the phase of the input signal with the phase of the output signal by the digital phase comparison means, and controls the digital variable frequency signal generation means with this comparison output;
The phase of the output signal of the digital variable frequency signal generating means is compared with the phase of the reference signal, the analog variable frequency signal generating means is controlled according to the comparison output, and the output of the analog variable frequency signal generating means is changed to the digital value. A digital PLL circuit configured to be provided with a second loop for inputting to a clock of the variable frequency signal generation means, wherein a noise shaper is provided in the first loop, and a digital output is provided by a comparison output of the digital phase comparison means. It is characterized in that the variable frequency signal generating means is controlled via a noise shaper.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

The digital PLL circuit according to the present invention is constructed, for example, as shown in FIG. In the digital PLL circuit shown in FIG. 1, an output clock CK (fck) having a frequency fck = nfref which is n times the frequency fref of the reference input signal S (fref) supplied to the reference signal input terminal 1 is supplied to the analog VCO 9 And the reference input signal S (fref) is supplied from the reference signal input terminal Tin1 and the analog V
The output clock CK (fck) formed by the CO10 is supplied through the feedback counter 2 to the digital phase comparator 3 and the reference of the frequency fp_ref >> fref sufficiently higher than the frequency fref of the reference input signal S (fref). The pilot signal S (fp_ref) is the reference pilot signal input terminal 2
And an analog phase comparator 7 to which an output clock CK (fck) generated by the analog VCO 10 is supplied via a variable frequency divider 7. Then, the comparison output of the analog phase comparator 8 is passed through the analog loop filter 9 as a control signal to the analog V
By being supplied to CO10, the analog VCO1
An inner loop adapted to feedback control the oscillation frequency of 0 (analog VCO 10 → variable frequency divider 7 → analog phase comparator 8 → analog loop filter 9 → analog VCO 10)
And the comparison output of the digital phase comparator 4 is supplied to the noise shaper 6 via the digital loop filter 5, and is supplied from the noise shaper 6 to the variable frequency divider 7 as frequency division control data. Thus, the outer loop for feedback controlling the oscillation frequency of the analog VCO 10 (analog VCO 10 → feedback counter 3 → digital phase comparator 4 → digital loop filter 5 → noise shaper 6 → variable frequency divider 7 → analog phase comparison Unit 8 → analog loop filter 9 → analog VCO
10) is configured. The feedback counter 3, digital phase comparator 4, digital loop filter 5, noise shaper 6 and variable frequency divider 7 in this digital PLL circuit constitute a digital processing block 20 that operates with a single clock.

The feedback counter 3 includes the analog VC.
The output clock CK (fck) generated by O10 is 1
/ N, which is the output clock CK (fck)
The n frequency-divided data is supplied to the digital phase comparator 4. In the digital PLL circuit of this embodiment, the feedback counter 3 sets, for example, n = 64, divides the output clock CK (fck) by 64, and divides 6-bit width data by 64 into the digital phase comparator 4 Shall be supplied to.

The digital phase comparator 4 compares the phase of the reference input signal S (fref) with the phase of the output clock CKout supplied via the feedback counter 3, and its phase comparison is performed. The phase error data is supplied as a comparison output to the noise shaper 6 via the digital loop filter 5.

The digital phase comparator 4 is shown in FIG.
As shown in FIG. 4, a phase detector for detecting the rising edge of the reference input signal S (fref) and a phase for generating the ramp wave-shaped phase error data from the frequency-divided n data of the output clock CKout by the feedback counter 3 An error generator 42 and a phase error latch circuit 43 that latches the phase error data generated by the phase error generator 42 at the timing of edge detection by the edge detector 41. In the digital phase comparator 4 having the configuration shown in FIG. 2, the edge detector 41
When detecting the rising edge of the reference input signal S (fref), supplies a detection pulse of one clock width to the phase error latch circuit 43. Further, the phase error generator 42 divides the output clock CKout by 64 in the feedback counter 3 by n = 64 to divide the divided clock by 64 into 6-bit wide 64 divided data, and when the 64 divided data is 0, 16 ( The error is converted into 5-bit phase error data having a gradient of -1 between 0 and 31 (± 15) as an error (+15 to -16). Then, the phase error latch circuit 43 latches the 5-bit phase error data at the timing of the rising edge detection pulse supplied from the edge detector 41,
Output as it is in 5 bit width. In the digital phase comparator 4 having the configuration shown in FIG. 2, the output clock CKout is used as the latch output by the phase error latch circuit 43.
Phase error data with unit resolution can be obtained.

Here, the digital phase comparator 4 has a ramp-wave-shaped reference input signal S as shown in FIG.
The A / D converter 44 that digitizes (fref), the decoding circuit 45 that decodes the frequency-divided n data by the feedback counter 3, and the phase error data obtained as a digital output by the A / D converter 44 are described above. A phase error latch circuit 46 that latches at the timing of the decode output by the decode circuit 45 may be used. In the digital phase comparator 4 having the configuration shown in FIG. 3, the phase error data having a resolution equal to or lower than the output clock CKout can be obtained as the latch output by the phase error latch circuit 46.

The comparison output of the digital phase comparator 4, that is, the phase error data, is supplied to the noise shaper 6 via the digital loop filter 5, and the variable frequency divider 7 is used as frequency division control data from the noise shaper 6. To be supplied to.

Further, the digital loop filter 5 is
A desired band fLoop of the outer loop for feedback controlling the oscillation frequency of the analog VCO 10 using the phase error data obtained as the comparison output by the digital phase comparator 4.
A proportional characteristic having a gain for obtaining <fref and an integral characteristic for eliminating a residual phase error regardless of the frequency of the reference input signal S (fref) are added. Here, in order to simplify the explanation, it is assumed to be through.

Further, the noise shaper 6 performs processing for changing the originally flat quantization noise spectrum into a high-frequency rising spectrum for the phase error data supplied from the digital phase comparator 4 through the digital loop filter 5. The primary noise shaper and the secondary noise shaper are used.

Here, the noise shaper 6 using the primary noise shaper has a general form as shown in FIG. 4, and a first adder 61 to which phase error data is supplied from the digital loop filter 5, The quantizer 63 and the second adder 64 to which the addition output of the first adder 61 is supplied
And a register 66 to which the addition output of the second adder 64 is supplied, and the output of the quantizer 63 is It is supplied to the second adder 62 via the (-1) multiplier 65, and the addition output of the second adder 62 is output by the register 66 at the timing of the enable signal from the variable frequency divider 7. The data is latched and supplied to the first adder 61.

The noise shaper 6 using the primary noise shaper having the above-mentioned structure is provided by the quantizer 63 from the + 6d.
An output having a noise spectrum with a frequency characteristic of B / oct is supplied to the variable frequency divider 7 as frequency division control data.

The addition output of the first adder 61 is set to z + 1 bits, and with respect to the addition output of this z + 1 bits, the quantizer 63 also discards the lower z bits on the LSB side and removes one bit on the MSB side. If you want to output,
A noise shaper 6 using a primary noise shaper omits the quantizer 63, the −1 multiplier 64 and the second adder 65, and as shown in FIG. The addition output of 61 can be constituted by a register 66 which is latched by the enable signal supplied from the variable frequency divider 7 and is supplied to the adder 61.

Further, the noise shaper 6 using the quadratic noise shaper has a general form as shown in FIG. 6, a first adder 61 to which phase error data is supplied from the digital loop filter 5, and a first adder 61. The second adder 62 to which the addition output of the first adder 61 is supplied, and the third adder 62 and the quantizer 63 and the third adder 62 to which the addition output of the second adder 62 is supplied. An adder 64, a first (-1) multiplier 65 to which the output of the quantizer 63 is supplied,
The first register 66 to which the addition output of the second adder 64 is supplied, and (2) the multiplier 67 and the second register 68 to which the output of the first register 66 is supplied, and the second register The second (-1) to which the output of the register 68 of
A multiplier 69, and the output of the quantizer 63 is passed through the first (−1) multiplier 65 to the third adder 64.
The output of the third adder 63 is latched by the first register 66 at the timing of the enable signal from the variable frequency divider 7, and is added via the (2) multiplier 67. While being supplied to the second adder 62, the latch output of the first register 66, that is, the addition output of the third adder 63 is latched by the register 68 at the timing of the enable signal from the variable frequency divider 7. Then, it is supplied to the first adder 61 through the second (−1) multiplier 69.

The noise shaper 6 using the secondary noise shaper having the above-mentioned configuration is +12 from the quantizer 63.
An output having a noise spectrum having a frequency characteristic of dB / oct is supplied to the variable frequency divider 7 as frequency division control data.

The addition output of the second adder 62 is set to z + 2 bits, and with respect to this addition output of z + 2 bits, the quantizer 63 discards the lower z bits on the LSB side and outputs 2 bits on the MSB side. If you do, 2
The noise shaper 6 using the next noise shaper omits the quantizer 63, the first (−1) multiplier 64, and the third adder 65, and as shown in FIG. Two
Of the adders 61 and 62 and the addition output of the adder 62 are latched by the enable signal supplied from the variable frequency divider 7 and are supplied to the second adder 62 via the multiplier 67 (2). The first register 66 and the second register 68 which supplies the latch output of the first register 66 to the first adder 61 via the (-1) multiplier 69.

The variable frequency divider 7 outputs the output clock CK (f from the analog VCO 10 at a frequency division ratio according to the frequency division control data supplied from the noise shaper 6.
ck) is divided, and the divided output is supplied to the analog phase comparator 8 as a feedback pilot signal S (fp_var).

The variable frequency divider 7 is constructed, for example, as shown in FIG. The variable frequency divider 7 shown in FIG. 8 includes a load value generation circuit 71 to which frequency division control data is supplied from the noise shaper 6 and a counter 72 that counts an output clock CK (fck) from the analog VCO 10.
And a decoder 73 to which the output of this counter 72 is supplied
And the load value generated by the load value generation circuit 71 according to the frequency division control data is transferred to the decoder 73.
By being loaded at the timing of the code output by the decoder 73, the output clock CK (fck) from the analog VCO 10 is provided as a decode output by the decoder 73 at a frequency division ratio according to the frequency division control data supplied from the noise shaper 6. Feedback pilot signal S (fp_va
r) is supplied to the analog phase comparator 8.

The analog phase comparator 8 receives the reference pilot signal S (fp_ref) supplied from the reference pilot signal input terminal 2 and the feedback pilot signal S (fp_var) supplied from the variable frequency divider 7. Of the feedback pilot signal S (f) with respect to the reference pilot signal S (fp_ref).
When the phase of p_var) is delayed, a positive phase error signal is supplied to the analog VCO 10 as a control signal via the analog loop filter 9, and a feedback pilot is supplied to the reference pilot signal S (fp_ref). When the phase of the signal S (fp_var) is advanced, a negative phase error signal is supplied to the analog VCO 10 as a control signal via the analog loop filter 9.

Further, the analog loop filter 9 is
Frequency characteristics for obtaining a desired band fp_Loop <fp_ref with a positive gain so that negative feedback is applied in an inner loop for feedback controlling the oscillation phase of the analog VCO 10 using the comparison output of the analog phase comparator 8 as a control signal. Consisting of a filter having

Further, the higher the comparison output of the analog phase comparator 8 supplied as a control signal through the analog loop filter 9, that is, the phase error, the higher the frequency fck of the output clock CK (fck) of the analog VCO 10 is. It consists of a voltage-controlled oscillator with the characteristic of increasing.

In the digital PLL circuit having such a configuration, the 1-bit frequency division control data K is supplied to the variable frequency divider 7 from the noise shaper 6 using the primary noise shaper shown in FIG. When controlling the division ratio,
For example, assuming that z = 5 bits, the adder 61 outputs z + 1 =
The LSB side 5 bits of the 6-bit addition output are latched by the register 66 at the timing of the 1-bit width enable signal supplied from the variable frequency divider 7. Then, when the frequency division control data K = 0, the load value L = 1 is loaded from the load value generation circuit 71 into the counter 72, thereby causing the variable frequency divider 7 to function as a third frequency divider, and When the frequency division control data K = 1, the variable frequency divider 7 is loaded by loading the load value L = 0 from the load value generation circuit 71 into the counter 72.
To function as a divide-by-four divider.

That is, when the phase error data supplied from the digital phase comparator 4 via the digital loop filter 5 is "0", the time series of the frequency division control data K output from the noise shaper 6 is , K = 0000
0000000000000000000000
00 is repeated, and the appearance rate of "1" is "0/3
The average value becomes "0/32" at "2". Further, the time series of the frequency division control data K when the phase error data is “1” is K = 000000000000000000000000
By repeating 0000000001, the appearance rate of "1" is "1/32" and the average value is "1/32".
Furthermore, the time series of the frequency division control data K when the phase error data is “2” is K = 000000000000
000100000000000000 is repeated, and the appearance rate of "1" is "2/32" and the average value is "2/32". Similarly, the time series of the frequency division control data K when the phase error data is "n" is "1".
Has an appearance rate of "(n-1) / 32" and an average value of "(n-
1) / 32 ”. As a result, the frequency division ratio of the variable frequency divider 7 is such that the appearance rate of "4" is "(n-1) / 32" and the average frequency division ratio is "3+ (n-1) / 32." As the phase error data increases in the positive direction, the average value of the number of interval clocks of the feedback pilot signal S (fp_var), that is, the average division ratio decreases.

By thus variably controlling the frequency division ratio of the variable frequency divider 7, the oscillation frequency of the analog VCO 10, that is, the frequency fck of the output clock CK (fck), is compared by the analog phase comparator 8. After the inner loop that feedback-controls the oscillation frequency of the analog VCO 10 by using the output as a control signal reaches a steady state, the frequency significantly determined by the value n of the phase error data and the frequency fp_ref of the reference pilot signal S (fp_ref). fck = {3+ (n
-1) / 32} × fp_ref.

That is, the digital PLL circuit is a VCO whose oscillation frequency is controlled by the phase error data supplied from the noise shaper 6 to the analog VCO 10 from the digital phase comparator 4 through the digital loop filter 5. The VCO, the feedback counter 3, the digital phase comparator 4, and the digital loop filter 5 constitute an outer loop PLL.
It functions as a heavy loop digital PLL circuit. In this double loop digital PLL circuit, the noise shaper 6 in the outer loop performs processing for changing the originally flat quantization noise spectrum into a high-range rising spectrum for the phase error data, and further, the analog loop in the inner loop. By suppressing the high frequency band with the filter 9, the oscillation output of the analog VCO 10, that is, the output clock CK
Phase jitter generated in (fck) can be reduced. That is, one wave of the feedback pilot signal S (fp_var) obtained by the variable frequency divider 7 has a jitter of fck clock unit, but is modulated by the noise shaper 6 so as to have a predetermined frequency in the long term. As a result, a high resolution frequency is expressed in the low frequency range, and the high frequency phase jitter can be suppressed by the analog loop filter 9 to be reduced.

Here, the 1-bit frequency division control data K is supplied from the noise shaper 6 using the primary noise shaper to the variable frequency divider 7 to control the frequency division ratio to 3 to 4 frequency divisions. In the double loop digital PLL circuit thus configured, the operation when the phase of the feedback counter 3 is delayed is shown in the timing chart of FIG. In the double loop digital PLL circuit, the input data of the noise shaper 6 is z = 6 bits, and the characteristic of the analog loop filter 3 is about 1 of the pilot frequency fp_var = fp_ref.
When the fixed data “1” is input to the noise shaper 6 with the low-pass characteristic having a cutoff frequency of / 16, that is, the frequency fck of the output clock CK (fck)
Is the frequency fp_ref of the reference pilot signal S (fp_ref)
Output clock CK (fck) obtained by the analog VCO 10 in the case where is multiplied by (3 + 1/64)
FIG. 10 shows the simulation result of the phase jitter of the above.

Further, in the case of supplying 2-bit frequency division control data K from the noise shaper 6 using the secondary noise shaper shown in FIG. 6 to the variable frequency divider 7 to control the frequency division ratio. Is, for example, with z = 5 bits, the first adder 61 obtains an addition output of z + 1 = 6 bits, and the second adder 62 obtains an addition output of z + 2 = 7 bits. The 5 bits on the LSB side of the added output of z + 2 = 7 bits by the device 62 are latched by the register 66 at the timing of the 1-bit width enable signal supplied from the variable frequency divider 7. And
The load value generation circuit 7 when the frequency division control data K = 0
By loading the load value L = 3 from 1 to the counter 72, the variable frequency divider 7 functions as a frequency divider by 2, and when the frequency division control data K = 1, it is loaded from the load value generation circuit 71. By loading the value L = 2 into the counter 72, the variable frequency divider 7 functions as a frequency divider by 3, and when the frequency division control data K = 2, the load value L = from the load value generation circuit 71. 1 for the counter 72
The variable frequency divider 7 is made to function as a frequency divider by 4 by loading the load value L from the load value generating circuit 71 to the counter 72 when the frequency dividing control data K = 3. The variable frequency divider 7 is made to function as a frequency divider 5 by loading the variable frequency divider 7 into the variable frequency divider 7.

That is, when the phase error data supplied from the digital phase comparator 4 via the digital loop filter 5 is "1", the time series of the frequency division control data K output from the noise shaper 6 is , K = 1111
11111111111111111111111111
11111111111111111111111111
By repeating 1111111111, the average value becomes "1 + 0/32." Further, the time series of the frequency division control data K when the phase error data is “1” is K = 1.
1111112012012020202102110
2111111111120112012020202
Since 1021021111111 is repeated, the average value becomes “1 + 1/32”. Further, the time series of the frequency division control data K when the phase error data is “2” is K = 111112020210211111120.
1202021111111111202021021
1111112012020211111 is repeated, and the average value becomes "2/32" at "1 + 2/32". Similarly, in the time series of the frequency division control data K when the phase error data is “n”, the appearance rate of “1” is “1+
At (n-1) / 32 ", the average value becomes" (n-1) / 32. " Accordingly, the frequency division ratio of the variable frequency divider 7 is
The appearance rate of "4" is "(n-1) / 32" and the average frequency division ratio is "3+ (n-1) / 32", and feedback is performed as the phase error data increases in the positive direction. The average value of the number of interval clocks of the pilot signal S (fp_var), that is, the average frequency division ratio becomes small.

By variably controlling the frequency division ratio of the variable frequency divider 7 in this way, the oscillation frequency of the analog VCO 10, that is, the frequency fck of the output clock CK (fck), is compared by the analog phase comparator 8. After the inner loop that feedback-controls the oscillation frequency of the analog VCO 10 using the output as a control signal reaches a steady state, the value f of the phase error data and the frequency fp_ref of the reference pilot signal S (fp_ref) are determined as the frequency fck that is significantly determined. = {3+ (n
-1) / 32} × fp_ref.

That is, this digital PLL circuit is a VCO whose oscillation frequency is controlled by the phase error data supplied from the noise shaper 6 to the analog VCO 10 from the digital phase comparator 4 through the digital loop filter 5. The VCO, the feedback counter 3, the digital phase comparator 4, and the digital loop filter 5 constitute an outer loop PLL.
It functions as a heavy loop digital PLL circuit.

Here, the 1-bit frequency division control data K is supplied from the noise shaper 6 using the secondary noise shaper to the variable frequency divider 7 to control the frequency division ratio to 2 to 5. In the double loop digital PLL circuit thus configured, the operation when the phase of the feedback counter 3 is delayed is shown in the timing chart of FIG. In the double loop digital PLL circuit, the input data of the noise shaper 6 is set to z = 6 bits, and the characteristic of the analog loop filter 3 is set to a low frequency range having a cutoff frequency of about 1/16 of the pilot frequency fp_var = fp_ref. With passage characteristics,
When the fixed data “1” is input to the noise shaper 6, that is, the frequency fck of the output clock CK (fck)
Is the frequency fp_ref of the reference pilot signal S (fp_ref)
Output clock CK (fck) obtained by the analog VCO 10 in the case where is multiplied by (3 + 1/64)
FIG. 12 shows the result of phase jitter simulation.

As is apparent from the simulation results shown in FIGS. 10 and 12, the double loop digital PLL circuit having the noise shaper 6 using the secondary noise shaper in the outer loop uses the primary noise shaper. It is possible to reduce the phase jitter of the output clock CK (fck) obtained by the analog VCO 10 as compared with the double loop digital PLL circuit having the noise shaper 6 in the outer loop.

[0049]

As described above, the digital P according to the present invention is used.
The LL circuit operates as a double-loop digital PLL circuit, and in the first loop, the phase of the input signal is compared with the phase of the output signal by the digital phase comparison means, and the comparison output is digitally output via the noise shaper. The variable frequency signal generating means is controlled, the phase of the output signal of the digital variable frequency signal generating means is compared with the phase of the reference signal in the second loop, and the analog variable frequency signal generating means is controlled according to the comparison output. Therefore, the high frequency noise can be suppressed by utilizing the frequency characteristic of the second loop, and the phase jitter generated in the output signal of the analog variable frequency signal generating means can be reduced.
In addition, the digital circuit portion can be operated with a single clock, which facilitates integration into an integrated circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital PLL circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a digital phase comparator in the digital PLL circuit.

FIG. 3 is a block diagram showing another configuration example of a digital phase comparator in the digital PLL circuit.

FIG. 4 is a block diagram showing a general configuration of a primary noise shaper used as a noise shaper in the digital PLL circuit.

FIG. 5 is a block diagram showing a specific configuration example of the primary noise shaper.

FIG. 6 is a block diagram showing a general configuration of a secondary noise shaper used as a noise shaper in the digital PLL circuit.

FIG. 7 is a block diagram showing a specific configuration example of the secondary noise shaper.

FIG. 8 is a block diagram showing a configuration example of a variable frequency divider in the digital PLL circuit.

9 is a dual-loop digital P having a noise shaper using the primary noise shaper shown in FIG. 5 in an outer loop.
7 is a timing chart showing an operation example of the LL circuit.

10 is a characteristic diagram showing a simulation result of phase jitter of an output clock obtained by a double loop digital PLL circuit having a noise shaper using the primary noise shaper shown in FIG. 5 in an outer loop.

11 is a timing chart showing an operation example of a dual-loop digital PLL circuit having a noise shaper using the secondary noise shaper shown in FIG. 7 in an outer loop.

12 is a characteristic diagram showing a simulation result of phase jitter of an output clock obtained by a double loop digital PLL circuit having a noise shaper using the secondary noise shaper shown in FIG. 7 in an outer loop.

FIG. 13 is a block diagram showing a configuration example of a conventional digital PLL circuit.

14 is a block diagram showing a configuration example of a digital phase comparator in the conventional digital PLL circuit shown in FIG.

FIG. 15 is a waveform diagram showing an operation example of the digital phase comparator.

FIG. 16 is a block diagram showing another configuration example of a conventional digital PLL circuit.

17 is a block diagram showing a configuration of a digital VCO in the conventional digital PLL circuit shown in FIG.

[Explanation of symbols]

 3 Feedback counter 4 Digital phase comparator 5 Digital loop filter 6 Noise shaper 7 Variable frequency divider 8 Analog phase comparator 9 Analog loop filter 10 Analog VCO

Claims (1)

[Claims] 1. A first loop for comparing the phase of an input signal with the phase of an output signal of an analog variable frequency signal generating means by a digital phase comparing means, and controlling the digital variable frequency signal generating means with this comparison output. The phase of the output signal of the digital variable frequency signal generating means and the phase of the reference signal are compared by the analog phase comparing means, and the analog variable frequency signal generating means is controlled according to the comparison output to generate the analog variable frequency signal generating means. And a second loop for inputting the output of the means to the clock of the digital variable frequency signal generation means, the digital PLL circuit having a noise shaper in the first loop, The digital variable frequency signal generating means is controlled by a comparison output of the means via a noise shaper. Digital PLL circuit.