JP2000022533A - Frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fraction frequency dividing synthesizer of simple control provided with excellent frequency purity capable of high-speed changeover. SOLUTION: In this frequency synthesizer for constituting a phase locked loop, a frequency dividing number setting means 11 supplies the set value of a frequency dividing number to a frequency dividing number switch means 8, the frequency dividing number switch means 8 cyclically switches the frequency dividing number to be supplied to a variable frequency divider 7 to generate a fraction frequency dividing number and a phase error compensation means 9 compensates a phase error due to the fraction frequency dividing number supplied to the frequency dividing number switch means 8. Then, a loop filter is provided with the high-speed loop filter 5b of a wide pass band and the low-speed loop filter 5a of a narrow pass band, and in the case of changing the output frequency of a voltage controlled oscillator, the pass band is widened in the high-speed loop filter 5b, the pass band is narrowed in the low-speed loop filter 5a and an output frequency is converged at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer used for a local oscillator of a communication device.

[0002]

2. Description of the Related Art Japanese Patent Laid-Open Publication No.
FIG. 6 shows an example of the configuration of a frequency synthesizer such as that shown in FIG. In the figure, 1 is a crystal oscillator, 2 is a reference frequency divider, 3 is a phase comparator, 4 is a charge pump,
7] is a loop filter, 6 is a VCO, 7 is a variable frequency divider,
15 is a division number switching circuit, 12 is a data selector, 16 is a division number data register, 19 is a retiming circuit, 20
Is a frequency dividing number generating means.

[0003] In the conventional state of the art, the crystal oscillator 1 is usually used.
The generated signal (frequency f _TCXO ) is frequency- _divided by the frequency divider Nc by the reference frequency divider 2 to obtain a reference frequency f _ref . This reference frequency _fref and the output of the variable frequency divider 7 (frequency fv)
Are compared by the phase comparator 3, the phase difference output from the phase comparator 3 is converted into a current by the charge pump 4, this current is converted into a voltage by the loop filter 17, and the VCO 6 is controlled by the voltage. The output of the VCO 6 is divided by the frequency divider (frequency f _out )
Is _{divided in} accordance with the division number N _k which is an integer output by the above, and is fed back to the phase comparator 3. Frequency interval f _r of the output frequency f _out at this time is equal to f _ref. At this time, the data selector 12 selects the frequency division number N _k output from the frequency division number data register 16. Further, the frequency division number data register 16 outputs the frequency division number _Nk set from outside. In the prior art, the loop filter is 2
The type of pass bandwidth can be set, and the narrower pass bandwidth is usually set.

Next, the operation at the time of switching the output frequency in the prior art will be described. If the output frequency f _out of the target was set to f _out = N · f _r equation 1, the frequency synthesizer of the prior art starts outputting frequency switching, set the N from the frequency division number data register 16 outside reference frequency The reference frequency f _ref is switched to f _refえ る by switching the frequency division number Nc of the frequency divider. f _{ref ＝=} f _out × M Expression 2 In addition to the above, a data selection signal for selecting the output of the frequency division switching circuit 15 is input to the data selector 12, and the frequency division number generating means 20 equivalently generates a frequency division number including a fraction. N ■ is generated, and a frequency interval of 1 / M of the reference frequency f _{ref ■} is obtained.

N ■ = int (N / M) + mod M (N) / M Equation 3 (int (N / M) is an integer part of N / M, and N and M are integers) where m = mod M (N) (m is an integer.) Assuming Equation 4, N ■ = int (N / M) + m / M Equation 5

[0006] Frequency synthesizer according the prior art by setting as described above it is possible to set the _■ M times the reference frequency f _ref while maintaining the same frequency interval f _r and normal even in the output frequency switching. In addition to the above, by setting the band of the loop filter 17 wide at the time of switching the output frequency, it is possible to quickly switch the output frequency to the target frequency.

Further, in the frequency synthesizer of the prior art, after the output frequency is switched to the target frequency for switching, the band of the loop filter 17 is returned to the normal state, and thereafter the variable frequency divider output from the frequency dividing number generating means 20 is output. _Is returned to N, which is an integer, and the reference frequency is returned to f _ref , thereby eliminating the influence of spurious generated by the fractional frequency division.

The frequency division number N ■ is set to m times while the pulse output from the variable frequency divider 7 is output M times.
By setting it to int (N / M) +1 and setting it to (M−m) times int (N / M), it is realized as an average frequency division number.

FIG. 7 shows a frequency dividing number generating means 2 according to the prior art.
0 is shown. 15 frequency division number switching circuit, 16 frequency division number data register, 12 data selector, adder 2
The adder 200 has carry-outs of 03 and 200, and a register 201. The register operates using the output of the variable frequency divider 7 as a clock and supplies the output to the adder 203. The data selector 12 selects the output of the frequency division number register 16 or the output of the adder 203 according to the data switching signal.

Next, a description will be given of an operation when generating a division number N ■ including a fraction. When the increment step of N ■ is 1 / M, the value that causes the carry-out of the adder 200 is M. When the output N ■ of the frequency division number switching circuit 15 is given by N ■ = N ■■ + m / M (N ■■ is an integer), the value m is input to one end of the input of the adder 200. The adder 200 adds m to the output of the register 201, and outputs a carry-out signal CO when the addition result reaches M or more.

Therefore, an overflow occurs once every M / m clocks, and a carry-out signal CO is output. This is set to 1 and added to N in the adder 203, and given as a frequency division number to the variable frequency divider. As a result, among the M / m clocks, M / m-1 times are divided by N ■■, and the remaining one is N ■■
It becomes +1. In this case, the average frequency division number is N ■■ + m
/ M, and a desired frequency division number can be obtained.

FIG. 8 shows a fractional frequency dividing operation when M = 4 and m = 1. The input terminal of the adder 200 is m
= 1 and the output of the register 201 are added. As shown by the waveform (b), the addition result of the adder 200 increases by one each time it is added as a clock, and when the clock whose value reaches 4 is added, the adder 200 outputs a carry-out signal. , The addition result of the adder 200 becomes 0. When this operation is performed, one every four clocks
The output of the adder 203 is incremented by 1, and the average frequency division number is N +
It becomes 1/4 (d). However, when the above configuration is adopted, a phase error as shown in FIG. The relationship between the phase error Q (n) and the phase error data Eθ (n) is represented by the following equation. 2πEθ (n) / M = Q (n) Equation 7

FIG. 9 shows waveforms at the input of the phase comparator 3 and the output of the charge pump 4. N + 1 frequency division is performed once every four times, and N + ／ frequency division is performed. However, because of the frequency division number switching, a phase error occurs between the waveforms (a) and (b). Since there is a relationship between f _out and f _ref , f _out = (N + ／) f _ref expression 8 1 / f _ref = (N + ／) · 1 / f _out expression 9 Generates a phase error of + f _out / 4, and every time the N + 1 frequency division is performed, -3f _out / 4
Is generated. The result of this time integration corresponds to the phase error Q described above.

In this prior art, the charge pump 4 is of a current output type, and the output gain of the charge pump 4 is I _P /
If 2π, a rectangular wave having an amplitude of I _P and a width equal to the phase error is generated at the output of the charge pump 4 due to the phase error. This square wave has the M times the period of the period of the output of the output or the variable frequency divider 7 of the reference divider 2 is input to the VCO through the loop filter, the reference frequency f _ref since modulates the output of the VCO Generates spurs at 1 / M intervals.

In order to avoid this, the frequency synthesizer according to the prior art returns the frequency division number to an integer after the output frequency is switched to the target frequency, thereby eliminating the influence of the above spurious.

[0016]

In the frequency synthesizer of the prior art, after the output frequency is switched to the target frequency, the frequency division number is returned to an integer, so that the phase comparison frequency decreases, and the operating speed of the PLL decreases. Would. Therefore, if there is a small frequency error or phase error in the output frequency at the moment when the frequency division number is returned to an integer, it is difficult to converge this at a high speed and complete the switching of the output frequency at high speed and completely. And the reference frequency is lowered, so that the frequency division number of the variable frequency divider increases, and the phase comparator, the variable frequency divider, the loop filter, etc. are vulnerable to external noise. There was a problem that it would.

[0017]

A frequency synthesizer according to a first aspect of the present invention includes a reference oscillator that oscillates at a predetermined frequency, a reference frequency divider that divides the output of the reference oscillator and outputs the frequency as a reference frequency. A voltage controlled oscillator whose oscillation frequency is controlled by a control voltage, a variable frequency divider for dividing the output of the oscillation frequency of the voltage controlled oscillator, an output of the variable frequency divider and an output of the reference frequency divider. And a charge pump that supplies a current based on the result of the phase comparison to the loop filter, and converts the current supplied by the charge pump into a voltage to control the voltage of the voltage-controlled oscillator. A loop filter to be output, a frequency dividing number to be given to the variable frequency divider, a frequency dividing number switching means for periodically generating a frequency dividing number, and a frequency dividing number setting in the frequency dividing number switching means. A frequency dividing number setting means for giving a value; and a phase error compensating means for compensating for a phase error caused by the fractional frequency dividing number given to the frequency dividing number switching means. When the output frequency of the voltage controlled oscillator is changed with a loop filter and a low-speed loop filter having a narrow pass band, the pass band is widened by the high-speed loop filter, and the pass band is narrowed by the low-speed loop filter. To converge the output frequency.

In a frequency synthesizer according to a second aspect of the present invention, the frequency division number switching means includes an adder and a register with a variable overflow value, and changes a reference frequency of the reference oscillator and a frequency division number switching pattern. Is to change.

In a frequency synthesizer according to a third aspect of the present invention, the frequency division number switching means includes a first adder having a variable overflow value and a second adder having a fixed overflow signal. One of the inputs of the first adder is bit-shifted during operation by the high-speed loop filter.

In the frequency synthesizer according to a fourth aspect of the present invention, the fractional frequency dividing means transmits the inputted frequency dividing number to the frequency dividing number switching means through the variable frequency divider to thereby provide the frequency division of the reference frequency. At the time of switching, the frequency division number is held.

In the frequency synthesizer according to a fifth aspect of the present invention, the frequency division number switching means controls the frequency division number of the variable frequency divider, performs frequency division, and outputs data of a generated phase error. The phase error compensating means includes a pulse width determining means for generating a rectangular wave according to the phase error data generated by the frequency dividing number switching means, an amplitude adjusting attenuator for adjusting the amplitude thereof, and a rectangular wave adjusted by the attenuator. And an output buffer for supplying the output buffer to the loop filter.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 shows a configuration example according to the present embodiment. In the figure, 1 is a crystal oscillator, 2 is a reference frequency divider, 3 is a phase comparator, 4 is a charge pump, 5a is a low-speed loop filter, 5b is a high-speed loop filter, 6 is a VCO, 7 is a variable frequency divider, 8 Is a frequency dividing means, 9 is a phase error compensating means, 10 is a fraction dividing means, 11
Is a frequency dividing number setting means, 18 is a reset generating means, 13 is a retiming circuit, 14 is a pulse generating means, and 15 is a charging buffer. The frequency division number setting a data value N of the fractional frequency division means 10, the value is a frequency division number setting data of the reference divider 2 N _ref, filter switching signal for setting the fast and slow modes is externally Has been entered.

The crystal oscillator 1, the reference frequency divider 2, the phase comparator 3, the charge pump 4, the VCO 6, and the variable frequency divider 7 among the components in the present embodiment are equivalent to those of the prior art. During normal operation (low-speed mode), the low-speed loop filter 5a is selected. During frequency switching (high-speed mode), the high-speed loop filter 5b is selected and used. The low-speed loop filter 5a and the high-speed loop filter 5b are selected by the re-timed filter switching signal. When the filter switching signal is high, the high-speed loop filter 5b is selected, and when the filter switching signal is low, the low-speed loop filter 5a is selected. I do.

The pulse generator 14 decodes the contents of the reference frequency divider 2 and _{divides the} frequency of the reference frequency divider 2 by N _ref.
A pulse is generated when the converted value matches the decoded value. The decode value of the pulse generation means 14 is set to N _ref / 2 equation 10 in the low-speed mode, and is set to N _ref / (2 · M) equation 11 in the high-speed mode. It can be obtained by halving the frequency division number given to the frequency divider 2.

The charge buffer 15 is turned on in the high-speed mode.
And the VCO control voltage V _vco output from the high speed loop filter 5b is transmitted to the low speed loop filter 5a.
Even in the high-speed mode, the output voltage of the low-speed loop filter 5a is kept at V _vco , so that the VCO control voltage does not change when switching from the high-speed loop filter 5b to the low-speed loop filter 5a. Reset generating means 1
8 generates a reset signal for resetting the integrator included in the frequency division number switching means 8 from the filter switching signal and the pulse of the pulse generation means 14. The filter switching signal retimed is connected to the frequency division number setting means 11, selects the frequency division number N _n of the frequency dividing number N _W and low-speed mode of high-speed mode.

[0026] The output frequency of the synthesizer of the present invention when set to f _out, set from the outside N with the following to the frequency interval f _r of the output frequency required relationship. f _out = f _r · N type 12 dividing number switching means 8 frequency division number is set in the variable frequency divider 7 at a low speed mode N _n is _{N n = int (N / M} ) + mod M (N) / M Equation 13 is set. Mod M (N) in the above equation is m in the description of the conventional example.

In the high-speed mode at the time of output frequency switching, Nw = int (N / (M · 2 ⁿ )) + (mod (M · 2 ⁿ ) (N)) / M Equation 14 is set. Mod (M · 2 ⁿ ) (N) is m in the description of the conventional example. In the present embodiment, N, M, n, L
Is a positive integer, and M = ^2L Expression 15. Therefore, the normal reference frequency f _refn input to the phase comparator and the reference frequency f at the time of output frequency switching are changed.
_refw has the following relationship: f _refn · 2 ⁿ = f _refw Equation 16 Since the phase comparison frequency becomes large in the high-speed mode at the time of switching the output frequency, by combining this with the high-speed loop filter 5b, the output frequency can be rapidly increased. Switching can be performed.

Embodiment 2 FIG. 2 shows the configuration of the frequency division number switching means 8 and the frequency division number setting means 11 in the present embodiment. An adder 200 generates a carry-out when the addition result becomes 2 ^{L + n} . A latch 201 operates in synchronization with a pulse generated by the pulse generation circuit 14. 2
A gate circuit 02 receives a reset signal and an addition result of the adder 200. An adder 203 adds the output Ni of the carry-out value switching means and the carry-out of the adder 200 as 1. Reference numeral 204 denotes a carry-out value selecting means, which is an adder 203 and an adder 2 according to a filter switching signal.
This is a selector for selecting a value to be given to 00. A register 205 holds a value N set from the outside.

Next, the operation of the frequency division number switching means 8 will be described. The frequency division number switching means 8 adds the value Add given to one of the inputs of the adder 200 and the output of the latch 201, and performs integration using the pulse generated by the pulse generation means 14 input to the latch 201 as a clock. This integration result is input to the phase error compensating means 9 as phase error data Eθ, and is used for phase error compensation described later. Adder 200 is Add
Is carried out, and when the addition result becomes 2 ^{L + n} or more, a carry-out occurs. The carry-out is set to 1 and the adder 203 adds it to Ni. By operating as described above, the dividing number including the fraction smaller than 1 is set in the fraction dividing means 10 as the average dividing number.

Next, the operation of the frequency division number setting means 11 will be described. When the dividing number N set from the outside is binary data of N (0: a) and the input of the carry-out value switching means of the adder 200 is Add (0: L + n-1), retiming is performed. When the set filter switching signal is Low, the carry-out value selecting means 204 connects N (0: L-1) of N (0: a) to Add (n-1: L + n-1) as m. Then, N (L: a) is connected to the adder 203 as Ni. By being connected as described above, the adder 20
The addition result that causes a carry-out of 0 is apparently 2 ^L
Ni, mod2 ^L (N) is given by Ni = int (N / 2 ^L ) Equation 17 m = mod2 ^L (N) Equation 18

The next, the frequency division number of the low-speed mode N _n is _{N n = int (N / 2} L) + mod2 L (N) / 2 L -type 19

## EQU1 ## From this, the resolution of the frequency division number of the fractional frequency dividing means 10 becomes 1/2 ^L.

When the retimed filter switching signal is Hi
At gh, the carry-out value selecting means 204 connects N (0: L + n-1) of N (0: a) to Add (0: L + n-1), and N (L + n: a) is connected to the adder 203. By the connection as described above, the addition result of the carry-out of the adder 200 is 2 ^{L + n} . Ni, mod2 ^L (N) is Ni = int (N / 2 ^{L + n} ) Equation 20 m = mod2 ^{L + n} (N) Equation 21

Thus, the frequency ^dividing number N _W in the high-speed mode is given by N _W = int (N / 2 ^{L + n} ) + mod 2 ^{L + n} (N) / 2 ^{L + n} Equation 22 From this, the resolution of the frequency division number of the fractional frequency ^dividing means 11 is 1/2 ^{L + n} .

When the filter switching signal retimed by the above configuration is High, Equation 22
Dividing number N _W becomes as shown in, filter switching signal retiming is frequency division number N _n represented by the formula 19 when the Low.

FIG. 3 shows a state of the output frequency switching operation in this embodiment. This description shows an example in which the output frequency is switched to f _out . (a) is a reference frequency generated by the reference frequency divider 2, (b) is an output of the fractional frequency dividing means 10, (c) is a filter switching signal, (d) is a frequency dividing number of the fractional frequency dividing means 10, ( e) is a pulse output from the pulse generation circuit, and (f) is a reset signal.

At the time point when the switching of t1 is started, a new value N is set in the frequency division number setting means 11, and at the same time, the filter switching signal becomes High, and the present synthesizer is set to the high-speed mode. filter switching signal retiming at time t2, the loop filter becomes High is changed from the low speed loop filter 5a to the high-speed loop filter 5b, the frequency division number of the fractional frequency division means 10 is changed from the N _n in N _W, Reference frequency divider 2
Is changed to N _ref / M, and the decoded value of the pulse generating means 14 is converted to N _ref / (2 · M). After the output frequency converges to f _out in the high-speed mode, at time t3, the filter switching signal goes low, and the synthesizer enters the low-speed mode. At time t4, the retimed filter switching signal becomes low, a reset signal is generated and input to the frequency division number switching means 8, the loop filter is returned to the low speed loop filter 5a, and the frequency division of the fraction frequency division means 11 is performed. The number is changed to N _n , the frequency division number of the reference frequency divider 2 is returned to N _ref , and the phase error data Eθ output from the frequency division number switching means 8 is reset. By operating as described above, the output frequency is quickly converged to f _out .

FIG. 4 illustrates the principle of canceling the phase error. (A) is phase error data Eθ (n), (b)
(C) is a phase error compensation signal for canceling the square wave of (c), (c) is a square wave generated at the output of the charge pump 4 due to a phase error due to fractional frequency division,
(D) is the residual signal after the phase error compensation, and (e) is the voltage V _L at the output of the loop filter. Also shown here is a state in which the frequency synthesizer of the present embodiment is synchronized with the output frequency f _out , and at this time, the control voltage of the VCO for outputting f _out is V _VCO .

The phase error compensating means 9 is provided to cancel the phase error Q (n) generated as described in the description of the prior art, and the phase error compensating signal is supplied to the low-speed loop filter 5.
Add to a. FIG. 5 shows details of the phase error compensating means 9.
The phase error compensating means 9 refers to the phase error data Eθ (n) and the contents of the reference frequency divider 2 to determine the phase error data Eθ
a pulse width determining unit 108 for generating a rectangular wave having a pulse width in units of 2 / f _TCXO in proportion to (n); and 109 for adjusting the amplitude of the rectangular wave output from the pulse width determining unit 108. An amplitude adjusting attenuator and an output buffer unit 110 for converting a rectangular wave output from the amplitude adjusting attenuator 109 into a rectangular wave having an amplitude of a current value, and a charge pump as shown in FIG. Connected to output.

The phase error compensation signal generated by this configuration has a rectangular wave having a constant width and an amplitude of a current value as a unit (hereinafter referred to as a unit rectangular wave). It is set by the amplitude adjustment attenuator 109 and the output buffer unit 110 so as to have the same current integral value as the rectangular wave due to the phase error when the error is 1 / (4f _out ). Assuming that the amplitude of the phase error compensation signal is I _C , the relationship with the amplitude I _P of the rectangular wave due to the phase error is as follows. I _P / (4f _out ) = 2I _c / f _TCXO

Such a unit rectangular wave is converted into pulse width determining means 1
08, the pulse width is changed by arranging the same number as the phase error data Eθ (n). With this operation, the rectangular wave due to the phase error and the current integrated value of the phase error compensation signal are output so as to be equal, and the rectangular wave due to the phase error cancels out except for the residual signal as shown in FIG. Looks like The frequency component of the residual signal has a much higher frequency distribution than the frequency component of the rectangular wave generated due to the phase error. It is easy to remove this residual signal by the low-pass characteristic of the PLL.

[0042]

According to the present invention, a phase error caused by a fractional frequency division is compensated in a normal state, spurious is suppressed, a fractional frequency division can be performed in a normal state, and a high reference frequency can be used. Since the frequency division number of the variable frequency divider becomes smaller, the phase divider, the variable frequency divider, the loop filter, and the like are more resistant to external noise. The synthesizer has two types of reference frequencies and two types of loop filters, a high-speed loop filter and a low-speed loop filter, to provide two states: a high-speed mode (when the output frequency is switched) and a low-speed mode (normal). Is provided, and the generated frequency can be quickly converged to the target frequency. Further, by configuring and operating the frequency division number setting means as in the present embodiment, it is not necessary to reset the frequency division number when switching between the high-speed mode and the low-speed mode, thereby simplifying the control.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a frequency synthesizer according to the present invention.

FIG. 2 is a configuration diagram of a division number switching unit and a division number setting unit according to the present invention.

FIG. 3 is a time waveform chart for explaining an operation at the time of output frequency switching in the present invention.

FIG. 4 is a time waveform diagram showing the principle of phase error compensation.

FIG. 5 is a configuration diagram illustrating a configuration of a phase error compensation unit.

FIG. 6 is a configuration diagram of a frequency synthesizer according to the related art.

FIG. 7 is a configuration diagram showing a configuration of a frequency division number generation unit in the related art.

FIG. 8 is a time waveform diagram showing a phase error due to fractional frequency division performed in the related art.

FIG. 9 is a time waveform diagram showing a phase error appearing in a charge pump in the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 crystal oscillator 2 reference frequency divider 3 phase comparator 4 charge pump 5 a low-speed loop filter 5 b high-speed loop filter 6 VCO 7 variable frequency divider 8 frequency division number switching means 9 phase error compensation means 10 fractional frequency division means 11 frequency division number Setting means 12 data selector 13 retiming circuit 14 pulse generating means 15 charging buffer 16 frequency dividing data register 17 loop filter 18 reset generating means 19 retiming circuit 20 frequency dividing number generating means 108 pulse width determining means 109 amplitude adjusting attenuator 110 output Buffer 200 Adder with carry-out 201 Register 202 Gate circuit 203 Adder 204 Carry-out value switching means 205 Register

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J004 BB03 CC02 CC06 CC09 DD10 DD14 DE01 DE02 5J060 AA04 BB10 CC01 CC21 CC42 DD13 DD32 GG01 GG09 HH02 KK03 KK23

Claims (5)

[Claims] A reference oscillator oscillating at a predetermined frequency;
A reference divider that divides the output of the reference oscillator to output a reference frequency, a voltage-controlled oscillator whose oscillation frequency is controlled by a control voltage, and a variable divider that divides the output of the oscillation frequency of this voltage-controlled oscillator A frequency comparator; a phase comparator that compares a phase difference between an output of the variable frequency divider and an output of the reference frequency divider; and a charge pump that converts a current amount based on a result of the phase comparison into a voltage. A loop filter that outputs a voltage converted by the charge pump as a control voltage of the voltage-controlled oscillator; and a frequency-dividing number switch that periodically switches a frequency-dividing number applied to the variable frequency divider to generate a fractional frequency-dividing number. Means, a frequency division number setting means for providing the frequency division number setting value to the frequency division number switching means, and a phase error compensation means for compensating for a phase error caused by the fraction frequency division number given to the frequency division number switching means. And having The loop filter has a high-speed loop filter with a wide pass band and a low-speed loop filter with a narrow pass band. When changing the output frequency of the voltage controlled oscillator, the pass band is widened by the high-speed loop filter, and the low-speed loop filter A frequency synthesizer characterized by narrowing a pass band and converging an output frequency at high speed. 2. The frequency division number switching means comprises an adder and a register whose overflow value is variable, and changes a reference frequency of the reference oscillator and a frequency division number switching pattern. The frequency synthesizer according to claim 1. 3. The frequency division number switching means includes a first adder having a variable overflow value and a second adder having a fixed overflow signal. 2. The frequency synthesizer according to claim 1, wherein one of the bits is bit-shifted during operation by the high-speed loop filter. 4. When the reference frequency is switched, the divided frequency is transmitted by the fractional frequency dividing means to the frequency dividing number switching means through the variable frequency divider. The frequency synthesizer according to claim 2, wherein the frequency synthesizer holds a number. 5. The frequency division number switching means controls switching of the frequency division number of the variable frequency divider, performs frequency division, and outputs data of a generated phase error. Pulse width determining means for generating a rectangular wave according to the phase error data generated by the frequency division number switching means, an amplitude adjusting attenuator for adjusting the amplitude thereof, and an output buffer for supplying the rectangular wave adjusted by the attenuator to the loop filter The frequency synthesizer according to claim 1, comprising: