JPH1093431A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify and miniaturize a PLL(phase locked loop) circuit and to reduce the cost for the circuit by comparing the output phase of a variable frequency divider with an outputting phase from a direct digital synthesizer so as to control the frequency of a voltage control oscillator to minimize an error. SOLUTION: The voltage control oscillator VCO 1 outputs a frequency fPLL based on the frequency of the minimum 1Hz step of a direct digital synthesizer DDS 2. Next the variable frequency divider 3 frequency-divides an originating frequency from VCO 1 into fDSS A phase comparator 4 compares an output phase from the divider 3 with an output phase from DDS 2 and controls the originating frequency of VCO 1 so as to minimize the phase error. Then the frequency dividing ratio and the originating frequency fDDS of the divider 3 are controlled by a set value set by a microcomputer. Thereby, a PLL. circuit can remarkably simplify the PLL, circuit and reduce the size and the cost of a device to mount for improving PLL performance by using the output frequency fDDS of DDS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DDS (Direct Digi
PLL (Phase-Locked Loo) using tal Synthesizer)
p) It relates to a circuit, particularly a PLL circuit used for a local oscillator of a so-called spot receiver (transmitter) or a full-wave receiver (transmitter).

[0002]

2. Description of the Related Art Generally, a first local oscillator of a spot receiver (transmitter) for performing communication at an unspecified certain frequency or a full-wave receiver (transmitter) capable of continuously changing a communication frequency is provided. A PLL frequency synthesizer is used. In recent years, a PLL circuit using DDS in combination with a PLL frequency synthesizer has been used for the purpose of shortening the PLL lock time.

FIG. 2 is a block diagram showing the configuration of a conventional PLL circuit of this type, which is a MF / HF band full-wave receiver.
2 shows a circuit used for a first local oscillator of a transmitter. PL
In the L circuit (A), f _REF × N is generated from the reference frequency f _REF by the phase comparator 1 and VCO 1 and the variable frequency divider. In the PLL circuit (B), the DDS, the frequency multiplier, the phase comparator, and the VCO 2 As a result, f _M + f _DDS is generated, mixed by the mixer MIX1, and the output f _PLL1 is output. f _PLL1 = f _REF × N + (f _M + f _DDS ) (1) Note that the division ratio N of the variable frequency divider and the output frequency of the DDS are controlled by setting a numerical value by a microcomputer (not shown). You.

For convenience of explanation, the reference frequency f _{REF is set} to 400 kHz, and the output frequency of the DDS is set to 555 kHz to 9 kHz.
If the signal varying 1Hz step of 55 kHz, by changing the value of the frequency division ratio N as shown in FIG. 3, the values of f _PLL1 changes at 400kHz step (reference frequency component), 555KHz in f _DDS It changes in steps of 1 Hz up to ９５955 kHz.

[0005]

A conventional PLL of this kind
The circuit is configured as described above, and changes in 1 Hz steps can be easily (fastly) performed. However, when the circuit configuration is large and mounted on a wireless transceiver, the device becomes large and expensive. In particular, when used in the above-mentioned spot receiver (transmitter), it is not always necessary to change the step by 1 Hz, so this problem becomes remarkable.

The present invention has been made to solve such a problem, and has as its object to provide a PLL circuit in which the number of components and the circuit are greatly simplified.

[0007]

A PLL circuit according to the present invention comprises a VCO, a variable frequency divider for varying the frequency division ratio under computer control to divide the oscillation frequency from the VCO, and a reference signal input thereto. The output frequency is varied in 1 Hz steps under the control of the computer, for example, the output frequency range is 1 Hz to 999.999.
kHz DDS and the output phase of the variable frequency divider
A phase comparator for comparing the output phase from the DS with a phase difference voltage detected by the phase comparator via the LFP;
O to control the oscillation frequency and output the same.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1A, reference numeral 1 denotes a VCO (voltage controlled oscillator), the output of which is a desired frequency f _PLL .
Reference numeral 2 denotes a DDS (Direct Digital Synthesizer) whose output frequency in this embodiment is a minimum of 1 Hz in steps of 1 Hz.
A device that outputs a frequency of ９９99.999 kHz is used.

Reference numeral 3 denotes a variable frequency divider whose frequency division ratio is varied by computer control to change the oscillation frequency from the VCO 1 to f.
_Divide to become _DDS . Reference numeral 4 denotes a phase comparator which compares the output phase from the variable frequency divider 3 with the output phase from the DDS 2 and controls the oscillation frequency of the VCO 1 so as to minimize the phase error. Reference numeral 5 denotes an LPF, and reference numeral 6 denotes a standard signal for DDS. In this embodiment, a 20 MHz crystal oscillator is used. Note that the frequency division ratio N of the variable frequency divider 3 and the output frequency f _DDS from the _DDS are controlled by numerical values set by a microcomputer (not shown).

The PLL circuit of the present invention is configured as described above, and the desired frequency f _PLL is f _PLL = N × f _DDS (2). (N: frequency division ratio f _DDS : output frequency of DDS2) That is, the PLL circuit of the present embodiment uses the output frequency f of DDS2 instead of the reference frequency f _REF of the conventional PLL circuit.
_The use of _DDS simplifies the circuit configuration. Therefore, to change the desired frequency f _PLL by 1 Hz, D
Although the numbers set for the DS2 and the variable frequency divider 3 are slightly more complicated than the conventional circuit shown in FIG. 2, the number of components and the circuit can be greatly simplified as compared with the conventional circuit.

As shown in FIG. 1B, if a MIX (mixer) 7 is inserted between the VCO 1 and the PFD (phase comparator) 4, the N value of the variable frequency divider 3 can be reduced. And C / N can be improved. When the MIX (mixer) 7 is inserted, the number of parts increases, but even in this case, the number of parts and the circuit scale can be greatly simplified as compared with the conventional circuit shown in FIG.

[0012]

As described above, the PLL circuit of the present invention can be much simpler than conventional circuits of this type, the size and cost of equipment to be mounted can be reduced, and the PLL performance can be improved. There is an effect that can be. In particular, when used as a local oscillator of a so-called spot receiver (transmitter), the effect becomes remarkable.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional PLL circuit of this type.

FIG. 3 is a diagram for explaining an operation of a conventional circuit.

[Explanation of symbols]

 1 VCO (Voltage Controlled Oscillator) 2 DDS (Direct Digital Synthesizer) 3 Variable frequency divider 4 Phase comparator 5 LPF 6 Standard signal for DDS 7 MIX (mixer)

Claims (1)

[Claims] 1. A DDS (Direct Digital System) used for a local oscillator of a wireless transceiver using an MF band or an HF band.
a PLL (Phase Locked Loop) circuit using a VCO, a variable frequency divider that varies the frequency division ratio under computer control and divides the oscillation frequency from the VCO,
DDS for changing the output frequency in 1 Hz steps under the control of the computer by inputting a reference signal
A phase comparator for comparing the output phase of the variable frequency divider with the output phase from the DDS; and inputting a voltage corresponding to the phase difference detected by the phase comparator to the VCO via an LPF, and And a means for controlling and outputting an oscillation frequency.