JPH01260926A - Pll oscillating circuit - Google Patents

Abstract

PURPOSE:To attain fast response speed and an excellent C/N by devising the circuit such that a voltage generating means generating a voltage in response to the content of a command is provided and an oscillation signal having a frequency in response to the voltage being the sum of its output voltage and an output voltage of a filter of a feedback loop is generated from an oscillation means. CONSTITUTION:When the content of a digital signal outputted from a control circuit 16 is changed by the key operation of a keyboard 15, the frequency division ratio of 1/N of a programmable frequency divider 12 is set newly in response to the content of the digital signal and a voltage V1 in response to the content of the digital signal is outputted from a D/A converter 21. The voltage V1 is added to an output voltage V2 of an LPF 14 at an adder 22, the result is outputted to a VCO 11 and the oscillated frequency f0 of the VCO 11 is changed immediately by the frequency only in response to the change in the voltage V1. The oscillation signal is subject to 1/N frequency division by the programmable frequency divider 12, the result is fed to a phase comparator 13, a voltage in response to the phase difference with a reference signal in a frequency fr is generated from the phase comparator 13, supplied to an LPF 14 to vary an output voltage V2 of the LPF 14.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a PLL (phase locked loop) oscillator circuit.

BACKGROUND ART An F having a local oscillation circuit using a conventional PLL oscillation circuit
The M receiver is shown in FIG. In this receiver, broadcast radio waves arriving at an antenna 1 are amplified by an RF (high frequency) amplifier 2 and supplied to a mixer 3. RF amplifier 2
The output signal is mixed with the oscillation signal output from the local oscillation circuit 4 in the mixer 3 and converted into an intermediate frequency signal. The intermediate frequency signal is sent to the FM detection circuit 6 via the IP amplifier 5.
The signals are supplied to and detected by the stereo demodulation circuit 7, and then stereo demodulated into left and right channel signals.

In the local oscillator circuit 4, VCO<voltage controlled oscillator)
11 oscillation signals are supplied to the mixer 3 and also to the programmable frequency divider 12.

The frequency-divided oscillation signal is phase-compared with a reference signal in a phase comparator 13 to obtain a voltage according to the phase difference, and the phase difference voltage is supplied to vCOll as a control voltage via an LPF (low-pass filter) 14. Ru. On the other hand, a keyboard 15 is provided for specifying an arbitrary receiving frequency, and a digital signal is supplied from the control circuit 16 to the programmable frequency divider 12 in accordance with the operation of the keyboard 15, and the frequency division ratio of the programmable frequency divider 12 is set. It is becoming fixed. The keyboard 15 includes, for example, up/down keys, preset selection keys, etc., and the control circuit 16 includes, for example,
Consists of a counter, clock generator and memory.

In the local oscillation circuit 4, the contents of the digital signal output from the control circuit 16 change by key operations such as up/down keys on the keyboard 15, and the frequency division ratio 1/N of the programmable frequency divider 12 changes depending on the digital signal. Determined according to the content.

Therefore, the frequency f of the oscillation signal of vCOll is fo/N
The oscillation signal of this frequency f, /N and the frequency f
The voltage corresponding to the phase difference with the reference signal of
arises from. This voltage is passed through LPF14 to vCOl
A feedback loop circuit is formed by supplying f.

When the phase difference between the oscillation signal of /N and the reference signal of frequency fr, that is, the frequency difference, is reduced, and the frequency and phase of the oscillation signal of fo/N and the reference signal match, it functions as a PLL oscillation circuit. is the locked state (f(, -Nfr
).

Incidentally, the LPF 14 is constituted by, for example, a time constant circuit consisting of an amplifier 17, resistors 18, 19, and a capacitor 20, as shown in FIG. Like this L
Since the PF 14 includes a capacitor, there is a limit to the response speed until the locked state is reached depending on the charging/discharging time of the capacitor. Furthermore, if the time constant of the LPF is made smaller, the response speed becomes faster, but there is a problem in that the C/N ratio deteriorates and good frequency stability cannot be obtained due to noise.

SUMMARY OF THE INVENTION An object of the present invention is to provide a PLL oscillation circuit that can increase response speed while obtaining a good C/N ratio.

The PLL oscillation circuit of the present invention includes an oscillation means for generating an oscillation signal with a frequency corresponding to an input voltage, a command means for generating a command specifying the oscillation frequency, and an oscillation signal at a frequency division ratio according to the content of the command. a frequency dividing means for dividing the frequency of the frequency dividing means, a phase comparing means for generating a voltage according to a phase difference between the output signal of the frequency dividing means and a reference signal, and extracting a low frequency component of the output voltage of the phase comparing means. a filter that generates a voltage according to the contents of the above-mentioned command, a voltage generating means that generates a voltage according to the content of the above-mentioned command, and an adding means that adds the output voltage of the filter and the output voltage of the voltage generating means and supplies the added voltage to the oscillating means as an input voltage. It is characterized by consisting of.

EXAMPLE Hereinafter, an example of the present invention will be described in detail with reference to FIG.

In the FM receiver having a local oscillation circuit to which the PLL oscillation circuit according to the present invention is applied, shown in FIG. 1, the same parts as in the receiver shown in FIG. 3 are indicated using the same symbols.
The programmable frequency divider 12 and the D/A converter 21 are connected to the output of the control circuit 16. D
/A converter 21 converts the digital signal output from control circuit 16 into a voltage signal and supplies it to adder 22 . The adder 22 adds the output voltage of the D/A converter 21 and the output voltage of the LPF 14. vColl at the output of the adder 22
is connected, and the output voltage of adder 22 is supplied to vCOll as a control voltage. The rest of the configuration is the same as the receiver shown in FIG.

Note that the adder 22 includes, for example, an operational amplifier 23 and resistors 24 to 28, as shown in FIG.

In this configuration, a digital signal output from the control circuit 16 is D/A converted by the D/A converter 21, and a voltage Vl corresponding to the content of the digital signal is supplied to the adder 22. The adder 22 adds the output voltage v1 of the D/A converter 21 and the output voltage v2 of the LPF 14,
Generates additional voltage v3 (=V+ +V2) and converts it to VcOl
supply l.

When the content of the digital signal output from the control circuit 16 changes due to a key operation on the keyboard 15, the frequency division ratio 1/N of the programmable frequency divider 12 is newly set according to the content of the digital signal, and the digital signal A voltage V1 corresponding to the content of is output from the D/A converter 21. The voltage (1) is added to the output voltage V2 of the LPF 14 in the adder 22 and output to VCOII. As a result, the oscillation frequency f of the VCOll immediately changes by a frequency corresponding to the amount of change in the voltage V1. The oscillation signal whose oscillation frequency fo has been changed is divided by a programmable frequency divider 12 to a frequency division ratio of 1/N and supplied to a phase comparator 13. A voltage corresponding to the phase difference between the oscillation signal of frequency fo/N and the reference signal of frequency fr is generated from the phase comparator 13 and supplied to the LPF 14 to change the output voltage V2 of the LPF 14. Therefore, due to the change in voltage v2, VC
The oscillation frequency of Oll is corrected, and the phase difference between the oscillation signal of f o /H and the reference signal of frequency fr is reduced.

Therefore, when the keyboard 15 is operated, first of all, the change in the output voltage V1 of the D/A converter 21 causes the VC
The oscillation frequency of OII becomes approximately equal to the desired oscillation frequency commanded from the keyboard 15, and then the oscillation frequency of VCOII is finely adjusted by the voltage V2 generated by the feedback loop circuit to become equal to the desired oscillation frequency, resulting in a locked state. That is, since the oscillation frequency f of the VCOll is almost determined by the output voltage V1 of the D/A converter 21, the change in the output voltage 2 of the LPF 14 may be small.

As described above, in the PLL oscillation circuit of the present invention, ■C
Forms a feedback loop circuit consisting of an oscillation means such as O, a frequency division means for obtaining a frequency division ratio according to the command contents of the command means, a phase comparison means, and a filter, and a voltage that generates a voltage according to the above command contents. The oscillation means has a generating means, and is configured so that the oscillating means generates an oscillation signal having a frequency corresponding to a voltage obtained by adding the output cuff IIS pressure of the voltage generating means and the output voltage of the filter. As a result, when the command content of the command means changes, the oscillation frequency of the oscillation means is almost immediately determined by the output voltage of the voltage generation means, so the change in the output voltage of a filter such as an LPF caused by the feedback loop circuit can be small. . Therefore, the response speed can be increased without reducing the time constant of the filter, and since a good C/N ratio can be obtained, frequency stability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram specifically showing the adder in FIG. 1, FIG. 3 is a block diagram showing a conventional example of a PLL oscillation circuit, and FIG. 4 is L in Figure 3.
FIG. 2 is a circuit diagram specifically showing a PF. Explanation of symbols of main parts 11...■CO 12...Programmable frequency divider 13...
- Comparator 14...LPF 15...Keyboard 16...Control circuit 21...D/A converter 22...・Adder applicant Pioneer Corporation

Claims (1)

[Claims] oscillation means for generating an oscillation signal with a frequency corresponding to the input voltage; command means for generating a command specifying the oscillation frequency;
a frequency dividing means for dividing the frequency of the oscillation signal by a frequency division ratio according to the contents of the command; and a phase comparison means for generating a voltage according to a phase difference between the output signal of the frequency dividing means and a reference signal. , a filter for extracting a low-frequency component of the output voltage of the phase comparison means, a voltage generation means for generating a voltage according to the contents of the command, and adding the output voltage of the filter and the output voltage of the voltage generation means. A PLL oscillation circuit comprising: an addition means for supplying the added voltage to the oscillation means as the input voltage.