JPH0311960Y2 - - Google Patents

Description

[Detailed description of the invention] (Field of industrial application) This invention is suitable for use in communication devices, especially receivers.
Regarding PLL (phase locked loop) circuits.

(Prior Art) In recent years, PLL circuits have come to be used in frequency control units of communication devices and the like, and their frequency stability has become extremely good.

We first developed the optimal PLL for this type of communication device.
A circuit was developed, and Figure 1 shows the main parts of this circuit.In this PLL circuit, the frequency division information from the frequency control circuit S can be varied by rotating the dial T. The frequency division ratio of the variable frequency divider VD (frequency division ratio is 1/7000 to 1/6001) is variable. Variable frequency divider VD
The signal from is compared with the signal from frequency divider _D1 , which will be described later, in comparator PD to control the oscillation frequency of the VCO (voltage controlled oscillator). The signal from the above VCO (70.0MHz to 60.001MHz) is sent to the next stage frequency divider D ₂
The frequency is divided into 1/100. On the other hand, the 9MHz signal obtained from the reference frequency oscillator OS (36MHz) via the frequency divider _D3 (X1/4) is added to the signal from the frequency divider _D2 (700KHz to 600KHz) (A), The output is input to the transmitter/receiver section R via a crystal filter F (9.7MHz to 9.6MHz).
The above 9MHz signal is input to the transmitting/receiving section R via the 1/2 frequency divider _D4 , and is also input to the above frequency divider _D1 (X1/450).
The frequency is divided to 10KHz and input to the comparator PD.

However, in the above method, the unlock time of the PLL (the time it takes for the oscillation frequency to complete moving from the lower limit to the upper limit) tends to be long, which tends to cause clicking noises at frequency edges and loss of lock. There was a problem.

In other words, in the above method, since the frequency change direction of the VCO is only in one direction as shown in Figure 2, the oscillation frequency changes at the frequency edge.
The frequency changes rapidly from 60.001MHz to 70MHz, making it difficult to lock the frequency. Furthermore, as shown in FIG. 3, the output waveform at _P2 has a sudden frequency change at the frequency edge, and this was supposed to be input to the transmitter/receiver section R as a factor in generating noise.

(Purpose of the invention) The present invention has been made in view of the above points, and its purpose is to provide a PLL circuit that can shorten unlock time and suppress click noise at frequency edges. It is in.

(Structure of the invention) In the PLL circuit according to the invention, the frequency division ratio of the variable frequency divider for variably controlling the frequency division ratio of the oscillation frequency output can be adjusted by rotating the dial in one direction. A PLL circuit whose frequency is variable based on information includes a phase comparator that compares the frequency output obtained by dividing the frequency output by the variable frequency divider with the output of a reference oscillator, and A first oscillator whose oscillation frequency can be changed back and forth depending on the output, second and third oscillators whose oscillation frequencies are different from each other, and a second oscillator whose oscillation frequency can be changed back and forth depending on the frequency change of the first oscillator. Alternatively, a switch section for selectively outputting the output signal from the third oscillator, and a mixer for mixing the signal from the switch section and a signal based on the signal from the first oscillator. We are prepared.

(Example) An example of the present invention will be described based on FIGS. 4 to 9.

In the figure, 1 is a first oscillator that can change the oscillation frequency back and forth, and the oscillation frequency (70.0MHz to 60.001MHz) is controlled by the frequency control section 2.
is now under control.

Reference numerals 3 and 4 indicate second and third oscillators having mutually different oscillation frequencies, which are set to 10.3MHz and 9MHz, respectively, in the embodiment. 5
is a switch unit for selecting and outputting the output signal from the second or third oscillator 3, 4;
It is adapted to be switched in accordance with a change in the oscillation frequency of the first oscillator. 6 is a mixer which outputs the output signal (10.3MHz) from the switch section 5.
or 9MHz) and a signal based on the signal from the first oscillator, which in the embodiment is a signal whose frequency is multiplied by 1/100 by the frequency divider 7 (0.7MHz to 0.6MHz). There is. The mixed signal passes through a filter 8 and is used as a signal source for a transmitter/receiver (not shown) or a measuring instrument (not shown).

Note that the third oscillator also serves as a reference oscillator for the frequency control section 2, and the frequency is divided by the frequency divider 21 (X1/
The 10KHz signal generated by the first oscillator 1 is combined with a signal from a variable frequency divider 22 for variable frequency division (1/7000 to 1/6001) of the output signal of the first oscillator 1 and a phase comparator 2.
3 to control the first oscillator 1. The frequency control section 2 and the switch section are controlled by a microcomputer C.

To explain an example of the operation in the above configuration, first, at the _P3 point, the oscillation frequency changes reciprocally as shown in Figure 5, but the band edge
At BE, the switch section 5 is switched,
Since the hetero frequency _P5 changes (FIG. 6), an output waveform similar to the conventional one is obtained at the output section _P5 .

If the above-mentioned operation is shown as a flowchart, as shown in FIG. 8, after the start 30, step 31
It is determined whether there is a dial T input (Y/N), and if there is a dial input, the amount of frequency change is calculated 32 based on the dial rotation angle. In step 33, the rotation direction and rotation angle of the dial are taken into the CPU, and the interval from a preset value to the next set value is a frequency increase interval, the next set interval is a frequency decrease interval, and so on.
Judging by the CPU, by the combination of the above dial rotation direction and frequency increase and decrease sections, a
It is determined whether it is a section or a section b, and if the direction is the direction shown in a, the branch is taken in the direction a, and conversely, if the direction of change is the direction shown in b, the branch is taken in the direction b. . In the branch a routine, frequency division is performed at a frequency division ratio of 7000→6001 (34), and after the frequency division information is output (35), the second or third oscillators 3, 4 are switched to the second oscillator 3 side in step 36. A signal to switch to is output.

On the other hand, in the branch b routine, the division ratio is 6000→
After frequency division of 6999 is performed 37 and frequency division information is output 38, a signal for switching the second or third oscillators 3, 4 to the third oscillator 4 is output in step 39. As described above, since the heterodyne frequency can be automatically switched according to the direction of frequency change of the first oscillator, the "dial rotation angle-frequency change" characteristic as shown in FIG. 7 can be obtained.

In the above-described embodiment, the frequency control is performed by the microcomputer C, but it goes without saying that the frequency may be set by a thumbwheel switch or the like.

Note that while the unlocking time using the circuit shown in FIG. 1 is several milliseconds to several tens of milliseconds, the circuit according to the present invention can shorten the unlocking time to about several hundred microseconds.

(Effect of the invention) According to the PLL circuit according to the invention, since the frequency of the first oscillator can be changed in the reciprocating direction, the unlocking time when switching from the upper limit to the lower limit of the PLL is changed. can be made extremely short, and the click noise at the frequency edge can be reduced. Furthermore, since the PLL is controlled by a continuously variable oscillator, it is difficult to lose lock and can always be maintained within the lock range. Therefore, if applied to a PLL with slow response, its stability can be greatly improved.

[Brief explanation of the drawing]

Figures 1 to 3 show conventional PLL circuits,
FIG. 1 is a block diagram, FIGS. 2 and 3 are waveform diagrams, and FIGS. 4 to 9 show embodiments of the PLL circuit according to the present invention. FIG. 7 is a waveform diagram, FIG. 8 is a flowchart, and FIG. 9 is a waveform diagram explaining the operating principle. 1: first oscillator, 2: frequency control section, 3: second oscillator, 4: third oscillator, 5: switch section, 6: mixer, C: microcomputer.

Claims (1)

[Claims for Utility Model Registration] The frequency division ratio of a variable frequency divider for variably controlling the frequency division ratio of the oscillation frequency output is varied by rotation angle information of the dial by rotating the dial in one direction. In a PLL circuit configured as shown in FIG. A first oscillator that can be changed back and forth, second and third oscillators whose oscillation frequencies are different from each other, and the second or third oscillator depending on whether the frequency of the first oscillator changes back and forth. a switch section for selectively outputting the output signal from the
A PLL comprising a mixer for mixing a signal from the switch section and a signal based on the signal from the first oscillator.
circuit.