JPH0631784Y2 - PLL circuit - Google Patents

Description

[Detailed Description of the Invention] [Purpose of Invention] (Industrial field of application) The present invention relates to a PLL circuit used in a wireless communication device and the like, and particularly, in accordance with the switching of modes such as SSB and FM. PL suitable for changing loop characteristics
Regarding the L circuit.

(Problems to be Solved by Conventional Techniques and Inventions) As a conventional PLL circuit used in a wireless communication device or the like, there is, for example, one shown in FIG.

The PLL circuit shown in FIG. 3 uses two or more low-pass filters (LPF-1, LPF-2) when changing the PLL loop characteristics in accordance with mode switching of SSB, FM, etc. I was switching and using it. Therefore, there is a problem in terms of cost due to a layout problem on the printed wiring board and an increase in the number of circuit components including the low pass filter.

This invention was made in view of the above points,
It is an object of the invention to provide a PLL circuit capable of changing the PLL loop characteristic by changing the reference frequency applied to the phase detector without increasing the number of circuit components such as a low pass filter.

“Configuration of Device” (Means for Solving the Problem) A PLL circuit according to the present invention is a PLL circuit of a wireless communication device having a plurality of modes including an FM mode and capable of mode selection, and the FM mode is selected. FM when you are
A VCO to be modulated, a first programmable divider that inputs a signal of a predetermined frequency and outputs a signal of a reference frequency divided by a first division ratio, and a signal of the oscillation frequency of the VCO are input. And a second programmable divider for outputting a signal of a frequency divided by a second division ratio, and inputting respective output signals of the first programmable divider and the second programmable divider, and Phase detector for detecting the phase difference between the signals of the VCO and the output of the phase detector
And a low-pass filter for outputting the output voltage to the PLL loop characteristic by changing both the first and second frequency division ratios according to the mode selection without changing the oscillation frequency of the VCO. .

(Operation) By changing the division ratio of the programmable divider for adding the oscillation frequency of the VCO to the phase detector and the division ratio of the programmable divider for making the reference frequency applied to the phase detector, the PLL loop The characteristics can be changed.

(Embodiment) An embodiment of the PLL circuit according to the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram showing the overall configuration, and FIG. 2 is a circuit diagram of an active filter.

In the figure, PD-1 is the oscillation frequency that is the basis of the reference frequency _r.
A programmable divider that divides _STD , for example, in accordance with the switching of modes such as SSB and FM.
The division ratio R is changed and added to the phase detector φ-DET. P ・ D-
2 is programmable that divides the VCO oscillation frequency _o
Programmable divider P
Similar to D-1, the frequency division ratio N is changed according to the mode switching, and the frequency _r is added to the phase detector φ-DET.

Further, the error signal E _o is output from the phase detector φ-DET and passed through the low pass filter LPF to become the DC voltage V _D , which changes the output frequency of the VCO.

A PLL loop is configured by the above circuits.

The circuit shown in FIG. 2 is a kind of low-pass filter and is an active filter.

The PLL loop constant when this is used, where W _{n is} the natural frequency of the loop and ξ is the damping factor of the loop, Kφ; Gain of phase detector φ-DET K _V ; Gain of VCO.

Considering an oscillation circuit of a constant frequency such as a local oscillation circuit in a VCO capable of FM modulation in the above configuration, in the case of FM mode, both programmable dividers P
When the frequency division ratio of D-2 is R and N, the PLL loop constant is represented by the above equation.

On the other hand, in the modes other than the FM mode, if the division ratios of both programmable dividers P · D-1 and P · D-2 are R ′ and N ′, the PLL loop constant W _n ′ (natural frequency of the loop)
And ξ ′ (the damping factor of the loop) is Then, assuming that the reference frequency is 1/4, R '= R
At / 4, the VCO is constant for the mode, so N '= N /
Become 4. Substituting this into the expression, Indicated by.

Therefore, if the reference frequency is multiplied by 1/4, the natural frequency W _n of the PLL loop constant and the damping factor ξ are each doubled, and the same frequency of the VCO but different PL
The characteristic of the L loop is obtained.

If the PLL loop constant is increased, the lockup time is reduced due to the characteristics of the PLL loop.
Response speed becomes faster.

"Effect of device" According to the PLL circuit of the present invention,
The characteristics of the PLL loop can be changed simply by changing the dividing ratio of the divider and switching the reference frequency. Therefore, by using the PLL circuit according to the present invention in a wireless communication device provided with various modes such as SSB and FM,
For FM mode, to increase the lock-up time, due to the low tone signal 88.5H _Z, etc.) frequency, it is possible to improve the distortion. In the case of other modes, to reduce the lock-up time As a result, a stable PLL loop system that is strong against vibration can be configured.
Further, unlike the conventional case, a plurality of low-pass filters are not required, so that the number of circuit parts can be reduced, the cost can be reduced, and the reliability of the circuit can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention, and FIG. 2 is a circuit diagram showing a concrete example of a low-pass filter used in the embodiment of FIG. FIG. 3 is a block diagram showing a main part of a conventional PLL circuit. P ・ D-1; First programmable divider P ・ D-2; Second programmable divider φ-DET; Phase detector LPF; Low pass filter VCO; Voltage controlled oscillator

Claims (1)

[Scope of utility model registration request] 1. A PLL circuit of a wireless communication device having a plurality of modes including an FM mode and capable of mode selection, wherein a VCO to which FM modulation is applied when the FM mode is selected and a signal of a predetermined frequency are input. And a first programmable divider that outputs a signal of a reference frequency divided by a first division ratio, and a frequency of a signal of the oscillation frequency of the VCO that is input and divided by a second division ratio. A second programmable divider for outputting a signal, and the first programmable divider
Of the programmable divider and the second programmable divider, and a phase detector for detecting a phase difference between the signals, and an output of the phase detector and output to the VCO And a low-pass filter for changing the PLL loop characteristic without changing the oscillation frequency of the VCO by changing both the first and second frequency division ratios according to mode selection. PLL circuit.