CA1066371A

CA1066371A - Demodulator for frequency-shift keying system

Info

Publication number: CA1066371A
Application number: CA315,666A
Authority: CA
Inventors: Rudolf Debuda
Original assignee: Canadian General Electric Co Ltd
Current assignee: General Electric Canada Co
Priority date: 1978-10-31
Filing date: 1978-10-31
Publication date: 1979-11-13

Abstract

ABSTRACT OF THE DISCLOSURE

A generator circuit employing binary logic elements is provided for use in generating a phase-coherent binary frequency-shift keyed signal having a frequency deviation ratio of one-half. Two embodiments of a self-synchronizing demodulator for demodulating an FSK signal of this type are provided. The self-synchronizing demodulator used in a system having an FSK signal of this type can receive faster pulse trains than can be received with any other binary FSK of PSK system of equal bandwidth, signal-to-noise ratio and error rate.

Description

Case 2086 s i637~l This lnvention relates to a communication system for transmitting and receiving binary signals.
Communication systems using binary signals usually encode the binary signals into either frequency steps (frequency-shift keying) or phase steps (phase-shift keying).
While known ~requency-shi~t keying (FSK) systems have -the advantage of simpler circuitry, it has been generally considered that phase-shift keying (PSK) has the advantage of better utilization of bandwidth and signal-to-noise ratio.
In cons~dering FSK systems, an important parameter which is frequently referred to is the frequency deviation ratio (symbol h). The frequency deviation ratio is de~ined as the chan~e in frequency (from mark to space) divided by the bit rate. Prior investigations by others have been made for FSK systems using small values of h, and in particular for the c~ses where h = 1 and h = 0.71. For h = 1, it is known that part of the signalling power is wasted by the presence of spectral lines at the two ` signalling frequencies~ Also, the case where h = 0.71 has been clai~ed to be optimum under certain conditions.
.
The case where h = 0O5 has previously been investigated to a degree. For example, it is known that an FSK signal having h = 0.5 has good spectral occupancy, with no spectral lines as with h ~ 1. In general, howe~er, an FSK system with ~ - 0.5 has previously not been considered to be as suitable as a PSK system.
I have found, however, that use of phase-coherent FSK haying h _ 0~5 has cextain advantages. This is particularl~ so when this FSK system is used with the optimal demodulator Which I have devised. This self-synchronizing demodulator used in an FSK system having h = 0.5 can receive faster pulse trains than can be received ~'. ' , ~, ,'. .

:
, , . . , ' ' ' Case 2086 B
-~663~
with any other binary FSK or PSK system of equal bandwlth, siynal-to-noise ratio and error rate.
In accordance with my invention, an apparatus is provided for generating a phase-coherent frequency-shift keyed signal which is keyed in response to a binary signal of a predetermined bit rate. A clock pulse generator provides a train of clock pulses having a repetition rate of n(n + 1) times the bit rate, where n is an integer. A scale-of-n counter connected to the clock pulse generator produces in response to the clock pulses a first train of pulses having a repetition rate of (n + 1) times the bit rate. A scale-of-(n + 1) counter connected to the clock pulse generator produces in response to the clock pulses a second train of pulses having a repetition rate of n times the bit rate~
A scale-of-n(n + 1) counter connected to the clock pulse generator produces in response to the clock pulses a train of control pulses having a repetition rate equal to the bit ~-rate. A logic circuit is connected to accept the binary signal and is connected also to the scale-of-n counter, to the scale-of-(n + 1) counter, to the scale-of-n(n + 1) counter and to a scale-of-two counter. The logic circuit is responsive to both the control pulses and the binary signal for providing the first train of pulses to the scale-of-two counter when the binary signal is in a first binary state and providing the second train of pulses to the scale-of-two counter when the binary signal is in a second binary state. The scale-of-two counter is responsive to the ~irst and second pulse trains to produce a frequency-shift keyed square wave. A ~ilter connected to the scale-of-two counter is responsive to the frequency-shift keyed square wave for pa.ssing the fundamental frequency component of the square wave and attenuating the second harmonic frequency ::

- 2 -.

. ~ , ~ .. , . . . , . : , . . .

Case 2086 B
~63'~ ~.
component ana the higher harmonic frequency componen-ts of the square wave, thus producing a phase-coherent frequency-shift keyed output signal. This output signal has a firs-t frequency when the binary signal is in the first binary state and a second frequency when the binary signal is in the second binary state. Also, the difference between the first frequency and the second frequency is equal to exactly one-half the bit rate.
In the apparatus described, the scale-of-n counter consists of a circulating register having n flip-flop stages, and the scale-of-(n + 1) counter consists of a circulating register having (n + 1) flip-flop stages. The scale-of-n (n + 1) co~mter consists of the n-stage circulating register, the (n + l)-stage circulating register, and a control AND
gate having a first input connected to the n-stage circulating register and a second input connected to the (n + l)-stage circulating register.
The logic circuit used includes a flip-flop having ` a first input connected to accept the binary signal, a second input connected through an inverter to the first input, and a timing input connected to accept the control pulses from the control AND gate. A first pulse train AND gate has a first input connected to the scale-of-n counter and a second input connected to a first output of the flip-flop.
A second pulse train AND gate has a first input connected to the scale-of-(n + 1) counter and a second input connected to a second output of the flip-flop. An OR gate has a first input connected to the first pulse train AND gate, a second input connected to the second pulse train AND gate, and an output connected to the scale-of-two counter. The flip-flop is responsive to each control pulse to switch to a first stable state or a second stable state in response to the i ~:

- 3 -. . .
.- . , :

Case 2086 B
~6~6~7~
binary signal being in the first binary state or the second binary state, respectively. The flip-flop is - adapted in the first stable state to provide at the first output an enabling signal to enable the first pulse train AND
gate to pass the first train of pulses by way of the OP~
gate to the scale-of-two counter. Also, the flip-flop is adapted in the second stable state to provide at the second output an enabling signal to enable the second pulse train AND gate to pass the second train of pulses by way of the OR gate to the scale-of-two counter.
In the apparatus disclosed, the convention followed is that the first binary state is a binary zero representing a space, and the second binary state is a binary one representing a mark. This convention is, of course, arbitrary. The apparatus can readily be used with the ` opposite convention.
Also in accordance with my invention, a self-synchronizing receiver is provided for demodulating a phase-coherent frequency-shift ke!yed (FSK) signal having a first frequency representing a first binary state of a binary signal and a second frequency representing a second binary state of the binary signal, where the difference between the first and second frequencies is equal to one-half the bit rate of the binary signal. The receiver consists of demodulator circuit means and frequency-doubler circuit means. The demodulator circuit means has an in-phase channel and a ~uadrature channel, each of the channels including integrate-dump circuit means. The frequency-doubler circuit means is responsive to the FSK signal for generating ." ~ .
reference signals, these reference signals including a ` carrier reference signal for each of the channels and a bit~synchronous clock reference signal. The demodulator . ~ . .
., :

Case 2086 B
63~7~

circuit means is responsive to the reference signals for demodulating the FSK signal.
The frequency-doubler circuit means includes first and second non-linear circuit means. The first non-linear circuit means is responsive to the FSK signal for producing first and second phase-coherent output signals having frequencies respectively at twice the first frequency and twice the second frequency. The second non-linear circuit means is responsive to the output signals for generating the reference signals. In the embodiments described, the second non-linear circuit means genera-tes - the carrier reference signal for each of the channels by generating two phase-coherent carrier reference signals.
The first non-linear circuit means consists of a frequency doubler and first ancl second phase-locked loops.
The frequency doubler is responsive to the FSK signal for producing an output containing a spectral line at twice the first frequency and a spectral line at twice the second frequency. The first phase-locked loop is connected to the frequency doubler and is responsive to the spectral line at twice the first frequency for producing the first output signal. Similarly, the second phase-locked loop is connected to the frequency doubler and is responsive to the spectral line at twice the second frequency for producing the second output signal.
. ` . . .
The second non-linear circuit means includes a balanced modulator, a low-pass filter and a hard limiter. ;
. ;. . .
The balanced modulator is connected to the two phase-locked :, , ~ . :
loops and is responsive to the two output signals for -30 producing the clock reference signal at the difference :; . .
frequency of the output signals. The low-pass filter is connected to the balanced modulator for selecting the ;i _ 5 _ --. ' .

.

Case 2086 B
37~
clock reference signal at this difference frequency. The hard limiter is connected to the low-pass filter for providing the clock reference signal as a square wave.
A first embodiment of the receiver makes use of the fact that the balanced modulator is further responsive to the two output signals for producing a high-frequency signal at the sum frequency of the output signals. In the first embodiment, the second non-linear circuit means further includes (in addition to the balanced modulator, the low-pass filter and the hard limiter) a high-pass filter and a divide-by-four freauency divider. The high-pass filter is connected to the balanced modulator for selecting the high-frequency signal at this sum frequency. The divide-by-four frequency divider is connected to the high-pass filter for producing the two phase-coherent carrier reference signals in the form cos 2 ~fot and sin 21rfot where t is time and fO is a frequency mid-way between the first frequency and the second frequency.
In a second embodiment (a preferred embodiment) of the receiver, the second non-linear circuit means further includes (in addition to the balanced modulator, the low pass filter and the hard limiter) first and second divide-by-two frequency dividers and first and second adder circuits. The first divide-by-two frequency divider is connected to the first phase-locked loop and is ; ,~ ,: .
responsive to the first output signal for producin~ a ' first divider output at the first frequency. The second divide-by-two frequency divider is connected to ; 30 the second phase-locked loop and is responsive to the ~;
second output signal for producing a second divider output at the second frequency. The first adder circuit is - 6 ~
.'-:, -~63~ Case 2086 ~

connected to the first and second divide-by-two frequency dividers for adding the first and second divider outputs and producing one of the phase-coherent carrier reference signals in the form (cos 2t) (cos ~fot) where t is timP
and T is the duration of one bit and fO is a fre~uency mid-way between the first frequency and the second frequency.
The second adder circuit is connected to the first and second divide-by~two frequency dividers for subtracting the first and second divider outputs and producing the other of the phase-coherent carrier reference signals in the form (sin ~L~ ) (sin 2~Tfot) .
; In drawings which illustrate embodiments of the invention:
Fig. 1 is a block diagram showing the circuit ` of an apparatus for generating a phase-coherent binary FSK signal having h = 0.5;
Fig. 2 shows the waveforms of voltages which : are present at various identified points in the circuit of Fig. l;
Fig. 3 is a graph showing the change of phase with time for a phase-coherent binary FSK signal; -~
Fig. 4 is a block diagram showing the circuit of one embodiment of a receiver for demodulating a ;
phase-coherent binary FSK signal having h = 0.5;
Fig. 5 is a block diagram showing the circuit of a preferred embodiment of a receiver for `~ demodulating a phase coherent binary FSK signal having h = 0~5; and -Fig. 6 (located on the third sheet of drawings) shows the waveforms of voltages which are present at certain identified points in the circuits of Figs. 4 and 5.

~ 7 '' ~.

Case 2086 B
~663~7~
Referring to Fig. 1, this block diagram shows the circuit of a particular embodiment of the FSK generator described earlier in this dislcosure. In the embodiment of Fig. 1, the integer n equals 4. Flip-flops 11, 12, 13 and 14 are connected to form a conventional circulating register having four stages. Similarly, flip-flops 15, 16, 17, 18 and l9 are connected as a five-stage circulating register. Clock pulse generator 20 provides a train of uniformly-spaced clock pulses (waveform B in Fig. 2) to drive each of the flip-flops 11 to 19 at its timing input T.
The repetition rate of the clock pulses is twenty times the bit rate. Thus, as shown in Fig. 2, there are twenty clock pulses for each bit of the modulating binary signal of waveform A. It will be noted that positive logic is used throughout this disclosure. That is, a logic "one" is ` shown as being more positive than a logic "zero".
Initially, each of the two circulating registers is arranged to have only one of its flip-flop stages set (i.e. a logic "one" at its Q output). Each clock pulse then advances the logic "one" by one stage of the register. ~
Waveforms C (Q output at flip-flop ll) and D (Q output ;~i at flip-flop 14) for the four-stage register show trains of uniformly-spaced pulses, one pulse being produced for every four clock pulses. The four-stage register thus acts as ~;
a scale-of-four counter for the clock pulses. Similarly, -~
waveforms ~E (Q output at flip-flop 15) and F (Q output at flip-flop 19) for the five-stage register show trains of ~ uniformly-spaced pulses, one pulse being produced for every `~ five clock pulses. The five-stage register thus acts as a -` 30 scale-of-five counter for the clock pulses.

:`, ': ' ',t , ."
_ ~8 _ ~

,. ~.:, ...

.. . .

, ' , ~ ' ' ~' ~ '., ' .' . '. . ' ~6~ Case 2086 B

Waveforms C and E are applied to the two inputs of control AND gate 21. Since pulses of waveforms C and E are in coincidence only once every twenty clock pulses, the output of control AND gate 21 (waveform G) provides one pulse for every twenty clock pulses (i.e. one pulse for each bit of waveform A).
Waveform G i5 applied to the timing input T
~ of flip-flop 22. The modulating binary signal (waveform A) ; is applied directly to the set input S of flip-flop 22, and through inverter 23 to the reset input R of flip-flop 22.
If waveform A is a mark (binary one) the flip-flop 22 is caused to assume its "set" state when the pulse of waveform G occurs, producing a "one" at the Q output(waveform H) and simultaneously a "zero" at the complementary Q output (waveform H). If waveform A is a space ~blnary zero) the ~` flip-flop 22 is "reset" when the pulse of waveform G
occurs, producing a "zero" at the Q output (waveform H) and a "one" at the Q output (waveform H).
Thus, for a space in waveform A, H is "one", enabling AND gate 24 (waveform K) to pass waveform D via OR gate 25 (waveform L) to flip-flop 26. Similarly, for a mark in waveform A, H is "one", enabling AND gate 27 (waveform J) to pass waveform F via OR gate 25 (waveform L) ; to flip-flop 26. The waveform L applied to flip-flop 26 has a fundamental frequency component which is an FSK signal having h = 1. Flip-flop 26 is connected as a scale-of two counter. Its output (waveform M) is thus at half the frequency of its input (waveform L). The value of h is also obviously divided by two, so that the fundamental frequency component of waveform M is an FSK signal having h = 0.5. The filter 28, which conveniently implemented as a low-pass filter, serves to pass the fundamental :~ _ g . . .

, . , ; - . . , Case 2086 B
3~

fre~uency c~mponent of waveform M and attenuate the harmonic frequency components. By inspection of waveform M it can readily be seen that the fundamental fre~uency component is phase-coherent. That is, in switching from one signalling frequency to the other there is no phase discontinuity in the waveform.
As is well known, in a phase-coherent FSK
signal the phase of the signal changes linearly with time during either a mark or a space. Fig. 3 shows the changes in phase which occur from time t = 0, at which time it is assumed the signal starts at centre frequency (i.e.
halfway bet~een the two signalling frequencies ). Assuming the convention that a space is higher in fre~uency than a mark, for each space the phase increases by~ h, and for each mark the phase decreases byl~h, the duration i-of one bit being shown in Fig. 3 as T. Since all phases are modulo 21~ , when h = 0.5 it is seen from Fig. 3 that the phase can take only two possible values of + 1r at odd multiples of T, ancl only two possible values of 0 and ~ at even multiples of T.
The receiver of my invention uses a phase ~` detector to establish the values of phase at each ~
`~ multiple of T. From Fig. 3 it is seen that if the phase ~-is known at each multiple of T, then a simple logic circuit can readily establish whether the change in phase in an interval between multiples of T was positive or negative, -and hence whether a space or a mark was received during the interval.
If the signal is received in white Gaussian noise, the optimal receiver structure is a clocked matched filter for instance implemented by an integrate-dump circuit ., . ':

lQ
' ~' -- : .. ..

~6~37~ Case 2086 B
in base band. The integrate-dump circuit performs an integration using the real part of the signal pre-envelope:

J(o) = S cos 2 T Re [~ (t)e ]dt and decides ~(o) = O if J~o) is positive or ~(o) = 1r if J(o) is negative.
That is, the integration is performed over a two-bit interval centered on an even multiple of T (in this case t = O). In the above formula, T = duration of one bit t = time ~(t) = pre-envelope of the FSX signal fO = centre frequency = 1 2 fl = frequency for a mark f2 ( ~ fl ) = frequency for a space.
Corresponding decisions in every second bit interval pair give the phase for even multiples of T, yielding half the information needed.
Similarly, the integrate-dump circuit also performs an integration using the imaginary part of the signal pre-envelope:

J (T) =~ sin1~2T Im [~(t) e ]dt and decides ~ (T) = 1t if J (T) is positive or ~ (T) = ~ 2 if J(T) is negative.

This integration is performed over a two-bit interval centered on an odd multiple of T(in this case t = T).
Corresponding decisions in every second bit interval pair give the phase for odd multiples of T, yielding the other half of the information needed. Conventional logic circuitry can thus re-construct the ori~inal modulating binary signal from the outputs of the integrate-dump circuits.

:

.. . ~ . . . . . . . . .. . . .

- Case 2086 B
3~
Referring to Fig. 4, one embodiment of the receiver circuit is shown. In this example, a receiver I.F.
amplifier 29 provides the signal to frequency doubler 30, which provides an output which is an FSK at h = 1 thus having spectral lines containing no modulation at 2fl and 2f2. Phase-locked loops 31 and 32 are tuned to 2fl and 2f2 respectively, providing output signals at these frequencies. The signals at 2fl and 2f2 are multiplied in balanced modulator 33, and the modulator output at (2f2 - 2fl ) or T is passed by low-pass filter 34 to hard limiter 35 where it is converted to a square wave and fed as signal V (see Fig. 6) to frequency divider 36.
Frequenc~ divider 36 has complementary outputs W and W
(see Fig. 6) applied to frequency dividers 37 and 38, whose complementary outputs X,X amd Y,Y are used to control gates 39, 40, 41 and 42 so that the integrate-dump circuits 43, 44, 45 and 46 are gated on at the correct times to integrate over the time intervals shown at their outputs. These integrations are performed in sequence cyclically, feeding output signals to combining logic ~7, which, as discussed previously, reconstructs the original modulating binary signal.
` The high frequency output from balanced -,~ modulator 33 ~i.e. 2f2 + 2f1 - 4fO) is passed by high-pass filter 48 to divide-by-four frequency divider 49 to give the phase-coherent carrier reference signals of the - form cos2~r~0t and sin2 1r fot. These reference signals are applied to balanced modulators 50 and 51 which also ~! receive the FSK signal from I.F. amplifier 29. The outputs of balanced modulators 50 and 51 are passed through low-pass filters 52 and 53 to remove the harmonics, and via the I-channel and the Q-channel to the gated ~ ' .

~637~ Case 2086 B

integrate-dump circuits as previously discllssed.
Fig. 5 shows a preferred embodiment of the receiver circuit, the difference between Fig. 4 and this embodiment being in the means to provide the phase-coherent carrier reference signals. As shown in Fig. 5, the outputs of phase-locked loops 31 and 32 are fed to frequency dividers 54 and 55 respectively. The outputs of frequency dividers 54 and 55 are added in adder 56 and subtracted in adder 57 to produce carrier reference signals of the form (cos ~ T ) (cos 2 ~fot ) for balanced modulator 50 and (sin 2 t ) (sin 2~ fot) for balanced modulator 51. Also, envelope demodulators 58 and 59 are included so that logic circuitry in frequency divider 36 can decide which of outputs W and W should go to the frequency dividers 37 and 38, thus ensuring that the integrate-dump circuits integra~e between envelope nulls for the signal in the corresponding channel.

; ".

. ':
,~ ' ' .

: -13 ;' ' .' ~
.

. .. : , .. : ... .:, , ~ . . .. . ~: . .

Claims

The embodiments of the invention in which an exclu-sive property or privilege is claimed are defined as follows:

1. A self-synchronizing receiver for demodulating a phase-coherent frequency-shift keyed signal having a first frequency representing a first binary state of a binary signal and a second frequency representing a second binary state of said binary signal, where the difference between said first and second frequencies is equal to one-half the bit rate of said binary signal, said receiver comprising: demodulator circuit means having an in-phase channel and a quadrature channel, and frequency-doubler circuit means responsive to said frequency-shift keyed signal for generating reference signals, said reference signals including a carrier reference signal for each of said channels and a bit-synchronous clock reference signal, and said demodulator circuit means being responsive to said frequency-shift keyed signal and said reference signals for demodulating said frequency-shift keyed signal.

2. The receiver of claim 1, wherein each of said channels of said demodulator circuit means includes integrate-dump circuit means.

3. The receiver of claim 2, wherein said frequency-doubler circuit means comprises: first non-linear circuit means responsive to said frequency-shift keyed signal for producing first and second phase-coherent output signals having frequencies respectively at twice said first frequency and twice said second frequency, and second non-linear circuit means responsive to said output signals for generating said reference signals.
4. The receiver of claim 3, wherein said second non-linear circuit means generates said carrier reference

Claim 4 continued.......
signal for each of said channels by generating two phase-coherent carrier reference signals.

5. The receiver of claim 4, wherein said first non-linear circuit means comprises: a frequency doubler responsive to said frequency-shift keyed signal for producing an output containing a spectral line at twice said first frequency and a spectral line at twice said second frequency, a first phase-locked loop connected to said frequency doubler and responsive to said spectral line at twice said first frequency for producing said first output signal, and a second phase-locked loop connected to said frequency doubler and responsive to said spectral line at twice said second frequency for producing said second output signal.

6. The receiver of claim 5, wherein said second non-linear circuit means comprises: a balanced modulator connected to said phase-locked loops and responsive to said output signals for producing said clock reference signal at the difference frequency of said output signals, a low-pass filter connected to said balanced modulator for selecting said clock reference signal at said difference frequency, and a hard limiter connected to said low-pass filter for providing said clock reference signal as a square wave.

7. The receiver of claim 6, wherein said balanced modulator is further responsive to said output signals for producing a high-frequency signal at the sum frequency of said output signals, and wherein said second non-linear circuit means further comprises: a high-pass filter connected to said balanced modulator for selecting said high-frequency signal at said sum frequency, and a divide-by-four frequency divider connected to said high-pass filter for producing said two phase-coherent carrier reference signals in the form cos 2 .pi. fot and sin 2 .pi. fot where t is time and fo is a frequency mid-way between said first frequency and said second frequency.

8. The receiver of claim 6, wherein said second non-linear circuit means further comprises: a first divide-by-two frequency divider connected to said first phase-locked loop and responsive to said first output signal for producing a first divider output at said first frequency, a second divide-by-two frequency divider connected to said second phase-locked loop and responsive to said second output signal for producing a second divider output at said second frequency, a first adder circuit connected to said first and second divide-by-two frequency dividers for adding said first and second divider outputs and producing one of said phase-coherent carrier reference signals in the form (cos 2.pi.fot) where t is time and T is the duration of one bit and fo is a frequency mid-way between said first frequency and said second frequency, and a second adder circuit connected to said first and second divide-by-two frequency dividers for subtracting said first and second divider outputs and producing the other of said phase-coherent carrier reference signals in the form (sin 2.pi.fot).