JPH0425577B2 - - Google Patents

Description

[Detailed Description of the Invention] Object of the Invention The present invention relates to an arithmetic device of an information processing system,
In particular, the present invention relates to an arithmetic unit suitable for converting integer type data to floating point type data.

Prior Art It is known that a conversion instruction for converting integer type data into floating point type data is effective for efficiently executing a type conversion instruction in a program coded in FORTRAN, for example. Conventionally, there are two ways to achieve this, one using software and the other using hardware. However, the method using software executes type conversion using a combination of instructions in several steps, making it possible to perform large-scale scientific calculations at high speed. This method was inefficient and clearly unsuitable when processing was desired.

The method using hardware involves preparing machine language for type conversion and directly executing it on hardware. An example of its configuration is shown in FIG. In FIG. 1, integer type data is sent from the main storage 10 to the general purpose arithmetic unit 70, where it is subjected to first processing.
The data is then sent to the floating point arithmetic unit 80 for second processing, and the result is written into the floating point register 51. The operation shown in FIG. 1 will be explained in detail below.

First, the data read from the main storage 10 is sent out via the storage bus 60, shifted by the aligner 20 so that it is left-justified under the control of the aligner controller 21, and transferred to the workpiece in the general-purpose arithmetic unit 70 via the operand bus 61. Register A
(WAR) Latch at 30. Next, if the data is negative, it is re-complemented by the complementer 32 and converted into positive number representation to create a mantissa part, which is latched into the second work register (WCR) 31 via the register 36. The register 36 is a circuit that holds intermediate results of operations.

Next, the mantissa part of the work register 31 is transferred to the shifter 3.
At the same time, the sign and exponent parts are generated by the constant generator 35, passed through the byte adder 34 and the intermediate result register 36, and then latched into the work register 31 again. In this case, the code is “0” if the original data is a positive number or zero,
If it is a negative number, it generates “1” and the exponent part is (4E) ₁₆
is generated and latched to the left in the work register 31. Figure 3 shows the work register 3 at this time.
1, the shaded area is the mantissa data, and the ``•'' mark is the decimal point position. Here, the reason for generating the constant (4E) ₁₆ in the exponent part is as shown in Figure 8a.
This is because the decimal point position of the integer type data was shifted to the left by 7 bytes, or 14 digits, and placed at the 1st byte from the left, as shown in . Furthermore, this is because the exponent part of floating point type data is an EXCESS-64 code.

After completing the above processing, the general-purpose arithmetic unit 70
sends intermediate progress via data path 62 to floating point unit 80. The floating point arithmetic unit 80 latches the sign and exponent part into a work register (FER) 45 and the mantissa part into a work register (FAR) 40.

In the floating point arithmetic unit 80, in the first cycle, the sign and exponent part of the data received by the complementer controller 49 are directly transferred to the register (FFR) 46, and the mantissa part is transferred to the complementer 41.
It instructs to transfer it to the register (FPAOR) 42 via . Next, the decoder 48 examines the consecutive "0"s in the upper part of the mantissa latched in the register 42, and the shifter 43 shifts the digits to the left and erases them. At the same time, the exponent part is subtracted by the amount shifted to the left, and the data is Post-normalize. This final result is written to floating point register 51 via register 44.

FIG. 4a shows a summary of the above processing for each machine cycle. As can be seen from FIG. 4a, in the conventional method using hardware, there is a time loss due to data transmission and reception between arithmetic units, and there is a limit to speeding up the process.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an arithmetic device that eliminates the drawbacks of the above-mentioned prior art and processes convert instructions for converting coefficient type data into floating point type data at high speed.

General Description of the Invention The present invention provides an aligner for extracting integer data from the read data when the read length from the memory is longer than the data length (in the following embodiment, the read length is 8 bytes and the data length is 4 bytes). When cutting out integer type data using an aligner from a predetermined length of data read from memory, by spacing the length of the exponent part in advance and packing it to the left, floating point type data (first The bytes are the exponent part and the rest are the mantissa part.

Embodiment of the Invention FIG. 2 shows an embodiment of the invention in which floating point arithmetic unit 80 of FIG. 1 is directly coupled to aligner 20. The integer type data read from the main storage 10 is sent out via the storage bus 60 and shifted to the left via the aligner 20.
In the figure, the aligner controller 21 shifts the integer type data so as to start from the second byte from the left. As a result, the integer type data is latched in the mantissa register (FAR) 40 in a left-aligned manner. Complementor control 49 is connected to register 40
If the integer type data latched is positive or zero, it passes through the complementer 41 as is, and if it is negative, it is complemented by the complementer 41 and converted into an integer representation. on the other hand,
Constant generator 50 generates constants for the sign and exponent parts. The sign is “0” when the data is positive or zero.
If it is negative, "1" is generated. The exponent yields (48) ₁₆ . where the exponent is a constant (48) ₁₆
The reason for this is, as shown in Figure 3b, 4
This is because when the integer type data of the bytes is left justified from the second byte, the decimal point position in the fifth byte is shifted to the left by 4 bytes, that is, 8 digits, to the first byte.

The post-normalization process is the same as in the case of FIG. 1, and the decoder 48 checks the consecutive 0s in the upper part of the mantissa latched in the register 42, and the shifter 43 shifts the digits to the left by that number and erases them. An arithmetic unit 47 subtracts the exponent part latched in the register 46 by the amount shifted by the left digit. The final result thus obtained is written to floating point register 51 via register 44. FIG. 4b summarizes the above processing.

Effects of the Invention As is clear from the above description, according to the present invention, when integer type data is cut out by an aligner from data of a predetermined length read from memory, floating point type data (first byte is an exponent part and the rest is a mantissa part), this has the effect of improving processing speed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional configuration example, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram comparing the contents of registers in the prior art and the present invention, and FIG. 4 is a diagram showing the conventional technology. FIG. 4 is a diagram for comparing the operation sequence of the present invention. 10... Main storage, 20... Aligner, 21... Aligner controller, 40,4
5...Work register, 41...Complementer, 42,
44, 46...Register, 43...Shifter, 47
... Arithmetic unit, 48 ... Decoder, 49 ... Complement controller, 50 ... Constant generator.

Claims (1)

[Claims] 1. In an arithmetic unit that converts integer type data to floating point type data, an aligner and a second length shorter than the first length included in the first length data read from memory a logic control unit that controls the aligner so that the integer type data is packed on the left side with a space equal to the length of the exponent part; and a logic control unit that controls the aligner so that the integer type data of a complementer that uses data as a mantissa part and performs complementation when the data in the mantissa part is negative; a constant generator that generates constants for the sign and exponent part;
a shifter for shifting the data of the mantissa from the complementer in order to erase the consecutive "0's" arranged in the upper part of the data, an arithmetic unit, and data for erasing the "0" consecutively arranged in the upper part of the data. and a logic control section that controls the arithmetic unit so as to correct the exponent part generated by the constant generation section by the number of digits shifted by the number of digits shifted.