JPS57168373A - Address converting device in picture processing - Google Patents

Address converting device in picture processing

Info

Publication number
JPS57168373A
JPS57168373A JP5335281A JP5335281A JPS57168373A JP S57168373 A JPS57168373 A JP S57168373A JP 5335281 A JP5335281 A JP 5335281A JP 5335281 A JP5335281 A JP 5335281A JP S57168373 A JPS57168373 A JP S57168373A
Authority
JP
Japan
Prior art keywords
address signal
coordinate
logical address
order
picture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5335281A
Other languages
Japanese (ja)
Inventor
Takashi Nagashima
Moritomo Matsuyama
Isao Fukushima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5335281A priority Critical patent/JPS57168373A/en
Publication of JPS57168373A publication Critical patent/JPS57168373A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management

Abstract

PURPOSE:To achieve address converting processing even for a long and a wide picture, by suitably selecting bits to be converted with each selecting circuit corresponding to the content of an input logical address signal and outputting a physical address signal corresponding a square picture. CONSTITUTION:In an example of an address converting circuit which contains a wide picture into a square picture storage device, X0,X1-X11 are inputted to an X coordinate 100 from the high-order bit of the X component of a logical address signal RL1 or RL2. Y components Y0,Y1-Y8 are inputted to a Y coordinate 101. When the input logical address signal is the RL1, gate signals GA, GB, GC and GD are given in the order of (0,1,0,0). In this case, as the correspondence between an outputted physical address signal RP1 and an input logical address signal RL1, the high-order bit X2 of the X coordinate address is located at the low-order of the Y coordinate address.
JP5335281A 1981-04-09 1981-04-09 Address converting device in picture processing Pending JPS57168373A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5335281A JPS57168373A (en) 1981-04-09 1981-04-09 Address converting device in picture processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5335281A JPS57168373A (en) 1981-04-09 1981-04-09 Address converting device in picture processing

Publications (1)

Publication Number Publication Date
JPS57168373A true JPS57168373A (en) 1982-10-16

Family

ID=12940386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5335281A Pending JPS57168373A (en) 1981-04-09 1981-04-09 Address converting device in picture processing

Country Status (1)

Country Link
JP (1) JPS57168373A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06176139A (en) * 1992-12-07 1994-06-24 Japan Small Corp Setting device for number of picture elements in picture processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06176139A (en) * 1992-12-07 1994-06-24 Japan Small Corp Setting device for number of picture elements in picture processor

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