JPS6449380A - Video gain control circuit - Google Patents

Video gain control circuit

Info

Publication number
JPS6449380A
JPS6449380A JP62205913A JP20591387A JPS6449380A JP S6449380 A JPS6449380 A JP S6449380A JP 62205913 A JP62205913 A JP 62205913A JP 20591387 A JP20591387 A JP 20591387A JP S6449380 A JPS6449380 A JP S6449380A
Authority
JP
Japan
Prior art keywords
ram
data
address
microcomputer
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62205913A
Other languages
Japanese (ja)
Inventor
Hideki Hisaie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62205913A priority Critical patent/JPS6449380A/en
Publication of JPS6449380A publication Critical patent/JPS6449380A/en
Pending legal-status Critical Current

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  • Television Receiver Circuits (AREA)

Abstract

PURPOSE:To nonlinearly attain the dizitization of a luminance and to attain the gain control of digital video data by using A/D converted video data as the address of a RAM and using the read data as the digital video data. CONSTITUTION:A bus buffer 21 normally outputs digital data 20 as a RAM address 22. When a selecting signal 27 outputted from a microcomputer 11 is significant, a microcomputer address 26 is outputted as the RAM address 22. In the same way, when the signal 27 is significant a RAM 23 writes RAM data 24 into the RAM. When the signal 27 is significant, a bus buffer 25 also supplies microcomputer data 28 as RAM data 24. The RAM 23 holds the converting tables f1-f4 to be shown with full lines and for example, the table f1 converts 0-x into 0-y and x-1023 into y-225. The microcomputer determines which table is selected depending on a target luminance and writes one of the converting tables accumulated in its own RAM into the RAM 23 by using the address 26, the signal 27 and data 28.
JP62205913A 1987-08-19 1987-08-19 Video gain control circuit Pending JPS6449380A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62205913A JPS6449380A (en) 1987-08-19 1987-08-19 Video gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62205913A JPS6449380A (en) 1987-08-19 1987-08-19 Video gain control circuit

Publications (1)

Publication Number Publication Date
JPS6449380A true JPS6449380A (en) 1989-02-23

Family

ID=16514822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62205913A Pending JPS6449380A (en) 1987-08-19 1987-08-19 Video gain control circuit

Country Status (1)

Country Link
JP (1) JPS6449380A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0451678A (en) * 1990-06-19 1992-02-20 Matsushita Electric Ind Co Ltd Gain control device
US9102004B2 (en) 2006-10-26 2015-08-11 Aro Welding Technologies Family of pliers for clamping plates having similar and preferably identical frames, and pliers from such family

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0451678A (en) * 1990-06-19 1992-02-20 Matsushita Electric Ind Co Ltd Gain control device
US9102004B2 (en) 2006-10-26 2015-08-11 Aro Welding Technologies Family of pliers for clamping plates having similar and preferably identical frames, and pliers from such family

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