JPS56124949A - Code converting circuit - Google Patents

Code converting circuit

Info

Publication number
JPS56124949A
JPS56124949A JP2875180A JP2875180A JPS56124949A JP S56124949 A JPS56124949 A JP S56124949A JP 2875180 A JP2875180 A JP 2875180A JP 2875180 A JP2875180 A JP 2875180A JP S56124949 A JPS56124949 A JP S56124949A
Authority
JP
Japan
Prior art keywords
address
circuit
bits
addition signal
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2875180A
Other languages
Japanese (ja)
Inventor
Mitsuo Kanai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2875180A priority Critical patent/JPS56124949A/en
Publication of JPS56124949A publication Critical patent/JPS56124949A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To unify an address in the same form so that the subsequent processing can be executed easily, by converting the address to a desired address by use of an addition signal generating circuit and an adder circuit, when the address which has been distributed by a series-parallel converting circuit is not a desired address. CONSTITUTION:The 6 bit address A of the 44 bit system is input to the input side of the code converting circuit 1, this address A is provided to the addition signal generating circuit 2 and the adder circuit 3, and an addition signal C corresponding to the value of the address A is generated from the generating circuit 2. And, the addition signal C is provided to the circuit 3, the low rank 4 bits of the circuit 3 are made a 4 bit information address of the 40 bit system, and the high rank 3 bits are output as the low rank 3 bits of the synchronizing address SA of 4 bits of the 40 bit system. And, the address is unified in the same form so that the subsequent processing is executed easily.
JP2875180A 1980-03-06 1980-03-06 Code converting circuit Pending JPS56124949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2875180A JPS56124949A (en) 1980-03-06 1980-03-06 Code converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2875180A JPS56124949A (en) 1980-03-06 1980-03-06 Code converting circuit

Publications (1)

Publication Number Publication Date
JPS56124949A true JPS56124949A (en) 1981-09-30

Family

ID=12257105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2875180A Pending JPS56124949A (en) 1980-03-06 1980-03-06 Code converting circuit

Country Status (1)

Country Link
JP (1) JPS56124949A (en)

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