JPS56101249A - Addition and subtraction system of pcm signal - Google Patents
Addition and subtraction system of pcm signalInfo
- Publication number
- JPS56101249A JPS56101249A JP307080A JP307080A JPS56101249A JP S56101249 A JPS56101249 A JP S56101249A JP 307080 A JP307080 A JP 307080A JP 307080 A JP307080 A JP 307080A JP S56101249 A JPS56101249 A JP S56101249A
- Authority
- JP
- Japan
- Prior art keywords
- addition
- input
- polarity
- absolute value
- amplitude
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/5057—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using table look-up; using programmable logic arrays
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
Abstract
PURPOSE:To make addition and subtraction of PCM signal, by providing only the addition table relating to the absolute value of input signal and indexing the addition table through the complement for one input signal according to the combined condition of the polarity of input signal. CONSTITUTION:Each polarity bit in two codes (a), (b), is input to a polarity processing circuit 34 with separation. Further, all the 7 bits in the amplitude bits of (a) and (b) are input to the addition table memory 33. The addition table memory 33 stores the result of addition of the absolute value of the amplitude of (a) and (b) in the form of codes in advance, and is indexed by taking the absolute value of two input signals (a) and (b) as the addresses. The output of the memory 33 is input to the polarity processing circuit 34 for the most significant bit only displaying carry, and it is directly output as the amplitude bit of the rest code or output in the form of complement via the complement generating circuit 32.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP307080A JPS56101249A (en) | 1980-01-17 | 1980-01-17 | Addition and subtraction system of pcm signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP307080A JPS56101249A (en) | 1980-01-17 | 1980-01-17 | Addition and subtraction system of pcm signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS56101249A true JPS56101249A (en) | 1981-08-13 |
Family
ID=11547066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP307080A Pending JPS56101249A (en) | 1980-01-17 | 1980-01-17 | Addition and subtraction system of pcm signal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56101249A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0750252A2 (en) * | 1990-10-30 | 1996-12-27 | Siemens Aktiengesellschaft | Device for comparing two binary coded data with at least 2-bit wide memories |
-
1980
- 1980-01-17 JP JP307080A patent/JPS56101249A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0750252A2 (en) * | 1990-10-30 | 1996-12-27 | Siemens Aktiengesellschaft | Device for comparing two binary coded data with at least 2-bit wide memories |
| EP0750252A3 (en) * | 1990-10-30 | 1997-02-19 | Siemens Ag | Device for comparing two binary coded data with at least 2-bit wide memories |
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