JPS54155733A - Page-address update processing system - Google Patents

Page-address update processing system

Info

Publication number
JPS54155733A
JPS54155733A JP6469278A JP6469278A JPS54155733A JP S54155733 A JPS54155733 A JP S54155733A JP 6469278 A JP6469278 A JP 6469278A JP 6469278 A JP6469278 A JP 6469278A JP S54155733 A JPS54155733 A JP S54155733A
Authority
JP
Japan
Prior art keywords
page
address
terminal
adder
full
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6469278A
Other languages
Japanese (ja)
Inventor
Eizo Fujisaki
Hideaki Ando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6469278A priority Critical patent/JPS54155733A/en
Publication of JPS54155733A publication Critical patent/JPS54155733A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation

Abstract

PURPOSE:To make it possible to determine the head-address information of the next page correctly in both page increase and decrease directions by using a full-adder. CONSTITUTION:The circuit consists of page addresses 1-0 and 5-0, intra-page addresses 1-1 and 5-5, full-adder 8, page increase and decrease direction indication FF9, inverter circuit group 10, one input terminal 11, the other input terminal 12, output terminal 13, and carry-in terminal 14. When the page update is carried out in the page increase direction, given logical page address 1 is supplied to terminal 11 of full-adder 8 to make all bits equivalent to address 1-0 ''0'' and then, bits complementary to ''2'' in terms of address 1-1 are supplied to terminal 12. As a result, logical address information 5 with address 5-0 represented by [3] on the decimal numeration system and address 5-1 by [0] is obtained, which is the head address of the next page.
JP6469278A 1978-05-30 1978-05-30 Page-address update processing system Pending JPS54155733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6469278A JPS54155733A (en) 1978-05-30 1978-05-30 Page-address update processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6469278A JPS54155733A (en) 1978-05-30 1978-05-30 Page-address update processing system

Publications (1)

Publication Number Publication Date
JPS54155733A true JPS54155733A (en) 1979-12-08

Family

ID=13265445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6469278A Pending JPS54155733A (en) 1978-05-30 1978-05-30 Page-address update processing system

Country Status (1)

Country Link
JP (1) JPS54155733A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5998254A (en) * 1982-11-26 1984-06-06 Fujitsu Ltd Address circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5998254A (en) * 1982-11-26 1984-06-06 Fujitsu Ltd Address circuit

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