JPS6457827A - 4/5 nrzi code conversion system - Google Patents

4/5 nrzi code conversion system

Info

Publication number
JPS6457827A
JPS6457827A JP21403887A JP21403887A JPS6457827A JP S6457827 A JPS6457827 A JP S6457827A JP 21403887 A JP21403887 A JP 21403887A JP 21403887 A JP21403887 A JP 21403887A JP S6457827 A JPS6457827 A JP S6457827A
Authority
JP
Japan
Prior art keywords
conversion
code
dsv
conversion table
main
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21403887A
Other languages
Japanese (ja)
Inventor
Tetsushi Itoi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP21403887A priority Critical patent/JPS6457827A/en
Publication of JPS6457827A publication Critical patent/JPS6457827A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To generate a high efficient code simply satisfying the RLLC rule by applying code conversion while prescribed main or sub conversion table properly so as to make the DSV integration value after conversion converged to zero. CONSTITUTION:A main conversion table being the collection of channel bits where DSV(Digital Sum Variation) being an index of a signal DC balance is -1 or +1, and a sub conversion table being the collection of channel bits where the DSV code of the channel bit converting the same data bit is inverted, are prepared. When the DSV integration value after conversion is within + or -5, the main conversion table is selected and in other cases, the code conversion is applied while either the main or the sub conversion table is selected properly so that the DSV integration value after conversion is converged into zero based on a data representing even/odd number of the inverted sign included in channel bit and the DSV integration before conversion. Thus, the high efficiency code satisfying RLLC(Run Length Limited Code) rule is generated simply.
JP21403887A 1987-08-27 1987-08-27 4/5 nrzi code conversion system Pending JPS6457827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21403887A JPS6457827A (en) 1987-08-27 1987-08-27 4/5 nrzi code conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21403887A JPS6457827A (en) 1987-08-27 1987-08-27 4/5 nrzi code conversion system

Publications (1)

Publication Number Publication Date
JPS6457827A true JPS6457827A (en) 1989-03-06

Family

ID=16649245

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21403887A Pending JPS6457827A (en) 1987-08-27 1987-08-27 4/5 nrzi code conversion system

Country Status (1)

Country Link
JP (1) JPS6457827A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012138147A (en) * 2010-12-27 2012-07-19 Hitachi Consumer Electronics Co Ltd Digital data recording and reproducing method, optical information recording and reproducing method, and optical information recording and reproducing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012138147A (en) * 2010-12-27 2012-07-19 Hitachi Consumer Electronics Co Ltd Digital data recording and reproducing method, optical information recording and reproducing method, and optical information recording and reproducing device

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