JPS57147116A - Binary information modulating system - Google Patents
Binary information modulating systemInfo
- Publication number
- JPS57147116A JPS57147116A JP56032675A JP3267581A JPS57147116A JP S57147116 A JPS57147116 A JP S57147116A JP 56032675 A JP56032675 A JP 56032675A JP 3267581 A JP3267581 A JP 3267581A JP S57147116 A JPS57147116 A JP S57147116A
- Authority
- JP
- Japan
- Prior art keywords
- bits
- bit
- output
- word
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
Abstract
PURPOSE:To minimize the extension of bit error, by indexing location information at the boundary inverting a binary data word to be split and making the coded efficiency greater through the bit coded word combined with the inverted data word and indexing. CONSTITUTION:Binary data train of 0, 1 is NRZI-midulated at 402 and blocked at 403 into data word in each m bit and given to a detector 405 and a buffer register 406. The detector 405 determines the inversion start bit (i-th), and outputs 0 to an output line of (i-1) lines of a decoder corresponding to (i-1)-bits and outputs 1 to the lines of (m-i+1) lines, and the outputs and the output of the register 406 are added to obtain an output inverting all the bits after the inversion start bits. Next, this output is coupled with the index in k bits from a coder 408 to form a code word in (n=m+k) bits and converted 411 into a serial data for transmission, and the original binary data is obtained through NRZI demodulation. Thus, the coding efficiency is increased and the extension in the bit error can be minimized.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56032675A JPS57147116A (en) | 1981-03-06 | 1981-03-06 | Binary information modulating system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56032675A JPS57147116A (en) | 1981-03-06 | 1981-03-06 | Binary information modulating system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57147116A true JPS57147116A (en) | 1982-09-10 |
Family
ID=12365444
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56032675A Pending JPS57147116A (en) | 1981-03-06 | 1981-03-06 | Binary information modulating system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57147116A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4837007A (en) * | 1971-09-14 | 1973-05-31 | ||
JPS56149854A (en) * | 1980-03-27 | 1981-11-19 | Western Electric Co | Digital transmission system |
-
1981
- 1981-03-06 JP JP56032675A patent/JPS57147116A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4837007A (en) * | 1971-09-14 | 1973-05-31 | ||
JPS56149854A (en) * | 1980-03-27 | 1981-11-19 | Western Electric Co | Digital transmission system |
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