JPS57106264A - System for data reproducing - Google Patents

System for data reproducing

Info

Publication number
JPS57106264A
JPS57106264A JP55181232A JP18123280A JPS57106264A JP S57106264 A JPS57106264 A JP S57106264A JP 55181232 A JP55181232 A JP 55181232A JP 18123280 A JP18123280 A JP 18123280A JP S57106264 A JPS57106264 A JP S57106264A
Authority
JP
Japan
Prior art keywords
data
circuit
clock
frequency
signal source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55181232A
Other languages
Japanese (ja)
Inventor
Akira Takeyama
Akimasa Yatsuhoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55181232A priority Critical patent/JPS57106264A/en
Publication of JPS57106264A publication Critical patent/JPS57106264A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To minimize the delay of a signal and reduce the scale of hardware to simplify reproducing control procedures, by making the frequency of a reproducing signal coincident with the frequency of a transmission clock signal source practically. CONSTITUTION:Input data 21 to a transmitting station 1 is sampled in an input circuit 3 by a clock f0 and is transmitted as a frequency f1 from a transmitting circuit 4. In a receiving station 2, data is sampled in a receiving circuit 5 by a clock f2 and is stored in a register 6. The number of data in the register 6 is supplied to a discriminating circuit 8 and is compared with thresholds TH and TL, and data is reproduced in accordance with the number of data by clocks fH and fL. At this time, a switching circuit 9 selects a signal source 14 of the clock fH when the number of data is larger than the threshold TH, and the circuit 9 selects a signal source of the clock fL when the number of data is smaller than the threshold TH. As the result, reproduced data 23 is obtained from an output circuit 7.
JP55181232A 1980-12-23 1980-12-23 System for data reproducing Pending JPS57106264A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55181232A JPS57106264A (en) 1980-12-23 1980-12-23 System for data reproducing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55181232A JPS57106264A (en) 1980-12-23 1980-12-23 System for data reproducing

Publications (1)

Publication Number Publication Date
JPS57106264A true JPS57106264A (en) 1982-07-02

Family

ID=16097107

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55181232A Pending JPS57106264A (en) 1980-12-23 1980-12-23 System for data reproducing

Country Status (1)

Country Link
JP (1) JPS57106264A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6145650A (en) * 1984-08-09 1986-03-05 Fujitsu Ltd Test system of frequency synchronization
FR2579047A1 (en) * 1985-03-15 1986-09-19 Cochennec Jean Yves Method for synchronisation by frequency compensation and device for implementing the method
FR2594277A1 (en) * 1986-02-13 1987-08-14 Houdoin Thierry Device for synchronising packets by dual phase-lock loop

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5012697A (en) * 1973-06-06 1975-02-08
JPS5429908A (en) * 1977-08-10 1979-03-06 Fujitsu Ltd Transmission control system in signal transmission system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5012697A (en) * 1973-06-06 1975-02-08
JPS5429908A (en) * 1977-08-10 1979-03-06 Fujitsu Ltd Transmission control system in signal transmission system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6145650A (en) * 1984-08-09 1986-03-05 Fujitsu Ltd Test system of frequency synchronization
FR2579047A1 (en) * 1985-03-15 1986-09-19 Cochennec Jean Yves Method for synchronisation by frequency compensation and device for implementing the method
FR2594277A1 (en) * 1986-02-13 1987-08-14 Houdoin Thierry Device for synchronising packets by dual phase-lock loop

Similar Documents

Publication Publication Date Title
JPS5731247A (en) Multiplexing tramsmission system
EP0111262A3 (en) Output multiplexer having one gate delay
JPS57106264A (en) System for data reproducing
JPS5686582A (en) Quantizing system at reception side for video information transmitter
JPS54161816A (en) Time-division type information transmission device
ES8107420A1 (en) Circuit arrangement for receiver-side clock recovery in digital synchronous information transmission.
GB1518006A (en) Frequency-selective signal receiver
JPS5710566A (en) Decoding circuit
JPS5758214A (en) Forming circuit of data sampling clock
SU876073A3 (en) Information decoding device
JPS57109444A (en) Telemeter device for pcm communication system
JPS5723346A (en) Code approving circuit
JPS5312215A (en) Pulse transfer circuit
SU621118A1 (en) Optimum receiver of bipulse signals
JPS5631247A (en) Communication system
JPS5689156A (en) Repeater for digital communication
JPS57108912A (en) Bus driving circuit
JPS5739368A (en) Fish detector for trawl fishing
JPS57115050A (en) Pulse signal transmitting and receiving circuit
JPS5758444A (en) Clock extracting system in dipulse code composite circuit
JPS5761328A (en) Detection circuit of coincidence of changing point of two kinds of clock signal
JPS5757093A (en) Sampling clock pulse generating circuit
JPS5734469A (en) Automatic gain control device in ultrasonic pulse transmission
JPS56119553A (en) Timing reproducing device
GB1026806A (en) Receiving apparatus and frequency shift keying systems for the utilisation thereof