JPS5734469A - Automatic gain control device in ultrasonic pulse transmission - Google Patents
Automatic gain control device in ultrasonic pulse transmissionInfo
- Publication number
- JPS5734469A JPS5734469A JP10930680A JP10930680A JPS5734469A JP S5734469 A JPS5734469 A JP S5734469A JP 10930680 A JP10930680 A JP 10930680A JP 10930680 A JP10930680 A JP 10930680A JP S5734469 A JPS5734469 A JP S5734469A
- Authority
- JP
- Japan
- Prior art keywords
- shift register
- signal
- clock
- output
- agc voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
- G01S7/523—Details of pulse systems
- G01S7/526—Receivers
- G01S7/529—Gain of receiver varied automatically during pulse-recurrence period
Abstract
PURPOSE:To avoid the effect of noises and the like inputted into a transmitting path by forming an AGC voltage from only the signal which is sent at every period and has a specified pulse width, a pulse interval, and a transmitting strength. CONSTITUTION:A clock (a) including a sampling signal which is synchronized with an incoming ultrasonic signal is formed by a clock generating circuit 6. The clock (a) is a clock signal for a shift register 9. A switching wave is formed by the clock generating circuit 6, and applied to a switching circuit 8. The input data to the shift register 9 is switched to the output signal of a comparator 5 from the output of the shift register 9. Therefore the content of the shift register 9 becomes a ''1'' level when the amplitude of the received signal is larger than the scheduled value under the state the transmission and reception are synchronized. The output of the shift register 9 is smoothed by an integrating circuit 10 to obtain the AGC voltage (e) and a receiving amplifier 2 is controlled by said AGC voltage (e).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10930680A JPS5734469A (en) | 1980-08-11 | 1980-08-11 | Automatic gain control device in ultrasonic pulse transmission |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10930680A JPS5734469A (en) | 1980-08-11 | 1980-08-11 | Automatic gain control device in ultrasonic pulse transmission |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5734469A true JPS5734469A (en) | 1982-02-24 |
JPS6222107B2 JPS6222107B2 (en) | 1987-05-15 |
Family
ID=14506846
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10930680A Granted JPS5734469A (en) | 1980-08-11 | 1980-08-11 | Automatic gain control device in ultrasonic pulse transmission |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5734469A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6268801U (en) * | 1985-10-21 | 1987-04-30 | ||
JPH0479705U (en) * | 1990-11-26 | 1992-07-10 |
-
1980
- 1980-08-11 JP JP10930680A patent/JPS5734469A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6222107B2 (en) | 1987-05-15 |
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