JPS6322503B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a decoding circuit, and particularly to a decoding circuit that decodes an FM code used in optical communications etc. into original data.

FIG. 1 is an electric circuit diagram showing an example of a conventional encoding circuit, FIG. 2 is a timing chart thereof, FIG. 3 is an electric circuit diagram showing an example of a conventional decoding circuit, and FIG. The figure shows the timing chart.

First, with reference to Figures 1 to 4, the conventional
The FM code encoding circuit and decoding circuit will be explained. Referring to FIG. 1, the FM encoding clock pulse (second
FIG. 2c, d) shows that the flip-flop 104 generates a transmitted clock pulse with a bit period T (FIG. 2c, d).
is converted to This transmit clock pulse is applied to the clock input of flip-flop 105. Bit period T input from input terminal 101
The transmission data A _i (Fig. 2 a) is transmitted from EXOR gate 1
It is applied to one input terminal of 08. The output signal of the flip-flop 105 is applied to the other input terminal of the EXOR gate 108. and,
The output of EXOR gate 108 is applied to the J input terminal of flip-flop 105 and the K input terminal via inverter 110. Then, the sending data A _i
and the transmit clock pulse generate a b _i (1) signal at the output of flip-flop 105.
This signal b _i (1) and transmission data A _i are combined into EXOR gate 1
08, b _i (2) shown in FIG. 2g is generated at the output terminal of this EXOR gate 108. And the flip-flop 105
The b _i (1) signal as the output of AND gate 107
EXOR gate 108
The b _i (2) signal as the output is applied to the other input terminal of the AND gate 106. A gate clock signal for b _i (1) is applied to the other input terminal of the AND gate 106 from the output of the flip-flop 104.
The other input terminal of the AND gate 107 receives the gate clock pulse for b _i (2) from the Q output terminal of the flip-flop 104. Therefore, the AND gate 106 derives the second half T/2 bit b _i (2) signal based on the gate clock pulse for b _i (2), and the AND gate 107 derives the b i (2) signal for b _i (1). A b _i (1) signal of the first half T/2 bits is derived based on the clock pulse. That is, the AND gate 107 generates b _i (1)=(2) _i-1 ...(1), and the AND gate 106 generates is generated and FM encoded as shown in Fig. 2h.

The transmission data series that has been FM encoded as described above is decoded into the original data by the decoding circuit shown in FIG. Received data sequences r ₀ (1), r ₀ (2), r ₁ (1), r ₁ (2), r corresponding to the FM encoded data encoded by the encoding circuit shown in FIG. ₂ (1), r ₂ (2)
…
...r _i (1), r _i (2)... are decoded by the decoding circuit. That is, this decoding circuit decodes the received sequence into original data based on a predetermined decoding algorithm A^ _i =r _i (1)r _i (2) . . . (3). that time,
It is necessary to generate a decoding clock pulse to distinguish between r _i (1) and r _i (2) and to accurately delimit the second bit in the received sequence. For this,
A receive timing clock pulse having a period of T/2 bits as shown in FIG. 4B is applied to the input terminal 302.
This clock pulse is applied to flip-flop 304 and converted into a clock pulse of T period shown in FIGS. 4c and 4d. Then, the Q and output of the flip-flop 304 and the timing clock pulse are applied to AND gates 309 and 310, and are used as decoding clock pulses in FIGS.
is generated. This decoding clock pulse e,
f and received sequence data are provided to a synchronization detection circuit 308. The synchronization detection circuit 308 uses the decoding clock pulses e and f and the received sequence data to set the gate 31 so that the first and second half bits in the received sequence data are separated correctly.
1,312,313,314 are opened and closed. Gates 311, 312, and 315 select decoding clock pulse e or f as the clock pulse to flip-flop 305.
Also, gates 313, 314, and 316 select signal f or e as a decoding clock pulse to flip-flops 306 and 307.
In other words, if the synchronization is correct, the pattern (0000, 1111, 1001, 0110) that cannot be created in the FM code
etc., so the synchronization detection circuit 308 constantly monitors this pattern, and if it detects this pattern, it assumes that the synchronization has been erroneous, and the gate 31
1, 312, 313, and 314 to switch between signals e and f as decoding clock pulses.

In this way, the decoding flip-flop 30
5, 306 and 307 are supplied with decoding clock pulses of correct synchronization. Then, from the Q output of the flip-flop 305, as shown in FIG.
r ₀ (1), r ₁ (1), r ₂ (1)... are T/2 from the received sequence data
Derived bits later. This data is then derived by flip-flop 306 with a further delay of T/2 bits. On the other hand, flip-flop 30
7, the data of the latter half of the received series data is derived with a delay of T bits from the received series data. and flip-flops 306 and 30
The Q output of 7 is provided by EXOR gate 317.
EXOR is performed, and the decoded output shown in FIG. 4j is derived from the output terminal 303.

The conventional decoding circuit configured as described above is
It is necessary to correctly discover the 2-bit break in the received sequence, and it is also necessary to detect erroneous synchronization patterns. Furthermore, if an error occurs in the data on the transmission path, there is a possibility that the decoding clock pulse will be switched by mistake.
There were drawbacks such as the inability to distinguish between consecutive 0s and 1s in the data.

Therefore, the main object of the present invention is to provide a decoding circuit that can decode data regardless of the division between the first half bit and the second half bit of received sequence data, in order to eliminate the above-mentioned drawbacks.

In summary, the present invention is capable of decoding a 1-bit period from a received data sequence consisting of a binary code having a T/2-bit period corresponding to a transmission data sequence consisting of a binary code having a T/2-bit period transmitted from an encoding circuit. T/2
Based on the clock pulse with a bit period, a decoding clock pulse with a T bit period is generated, and the decoding clock pulse with a period of T/2 is generated.
Based on the clock pulse of the bit period and the decoding clock pulse, a pulse corresponding to the second half of the T/2 bit period is generated, and based on this pulse, the binary code of the second half bit is selected from the received sequence data, and the decoding clock pulse is generated. The binary code of the selected second half bit is delayed by T bit periods based on the binary code of the second half bit of the previous time that was delayed and the binary code of the current second half bit that was selected previously. The original data is then decoded using the

The above objects and other objects and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.

FIG. 5 is an electrical circuit diagram of an embodiment of the present invention. In this configuration, received sequence data with a bit period T/2 is inputted via the input terminal 501 to the K input terminal via the J input terminal of the flip-flop 506 and the inverter 510.
given to the input end. On the other hand, the received timing clock pulse through the input terminal 502 is ANDed with the clock pulse input terminal of the flip-flop 505 for generating the decoding timing clock pulse.
It is applied to one input terminal of gate 509. The Q output of flip-flop 505 is connected to AND gate 509.
, the clock pulse input terminal of flip-flop 507 , and output terminal 504 . The output signal of AND gate 509 is applied to the clock pulse input of flip-flop 506, and the Q output signal of flip-flop 506 is applied to the J input of flip-flop 507 and one input of EXOR gate 508. Also,
The output signal of flip-flop 506 is applied to the K input of flip-flop 507. The Q output signal of this flip-flop 507 is applied to the other input terminal of the EXOR gate 508.
The output signal of EXOR gate 508 is inverter 5
11 from the output end 503.

FIG. 6 is a timing chart for explaining the operation of FIG. 5.

Next, the specific operation of one embodiment of the present invention will be described with reference to FIGS. 5 and 6. Also, before explaining the circuit operation, the expression regarding encoding will be modified. Assuming that the conventional encoding circuit shown in FIG. ) From the formula It is transformed into. b _i (1) in this equation (4) is the EXOR of the data A _i-1 transmitted one bit before and the inverted version of the first half bit one bit before.
b _i (2) in the formula is the EXOR of the data A _i to be sent this time and the inverted version of the second half bit of the previous bit.
It can be seen that it is.

In this way, the encoding circuit performs FM encoding and at the same time performs differential encoding as shown in equations (4) and (5) for b _i (1) and b _i (2), respectively. It's summery.

In operation, when the timing clock pulse shown in FIG. 4b is applied to flip-flop 505, the pulse shown in FIG. 6c is obtained at its Q output. This pulse is led out from the output terminal 504. Also, the Q of flip-flop 505
The output signal and the original timing clock pulse are
By being fed to AND gate 509,
The output signal of this AND gate 509 is
This is the clock pulse for selecting the latter half of the bit shown in FIG. By applying this clock pulse d to flip-flop 506,
The flip-flop 506 receives received sequence data r _i (1),
The second half bit of r _i (2), that is, r _i (2) is selected.
Note that the output signal of the flip-flop 505 and the timing clock pulse are connected to an AND gate 509.
, the flip-flop 506 can also select the first half bit r _i (1). The signal r _i (2) selected by the flip-flop 506 is applied to the flip-flop 507, and since the clock pulse c from the flip-flop 505 is applied to the flip-flop 507, the Q output of the flip-flop 507 is delayed by the period T. The calculated r(2) _i-1 is obtained. Then, r _i (2) as the Q output of the flip-flop 506 and r (2) _i-1 as the Q output of the flip-flop 507 are EXORed by the EXOR gate 508 and inverted by the inverter 511. It is decoded as follows. That is, the flip-flop 506 detects the second half bits of the current data, the flip-flop 507 detects the last half bit data, and EXORs these data.
If EXOR is performed by the gate 508, the original data can be decoded. The above is the operation of the encoding and decoding circuit according to an embodiment of the present invention, and the fact that the FM code can be asynchronously decoded by decoding as described above will be explained below using a polynomial expression.

Expressing equations (4) and (5) obtained from the encoding algorithm as polynomials, where x represents a delay of T/2, (1+x ² )b ₁ (x ² ) = x ² A(x ² ) + b ₀ (1) + J (x ² ) + 1 ... (7) (1 + x ² ) b ₂ (x ² ) = A (x ² ) + A ₀ + b ₀ (2) + J (x ² ) + 1 ... ( 8) becomes. However, A (x ² ) = A ₀ + A ₁ x ² + A ₂ x ⁴ +… (9) b ₁ (x ² ) = b ₀ (1)x ² + b ₂ (1)x ⁴ +…… (10) b ₂ (x ² )=b ₀ (2)+b ₁ (2)x ² +b ₂ (2)x ⁴ +… ……(11) J(x ² )=1+x ² +x ⁴ … ……( 12), and b ₀ (1) and b ₀ (2) are the initial states of the encoding flip-flop 105 shown in FIG. Therefore, the FM encoded data sequence b(x) is expressed as b(x)△=b ₁ (x ² ) + xb ₂ (x ² )...(13) When e(x) is added, the reception sequence r(x) becomes r(x)△= _r1 ( ^x2 )+ _xr2 ( ^x2 )...(14) e(x), where L is the delay between sending and receiving )+b(x)・x ^L ...(15) Here, e(x)△=e ₁ (x ² )+xe ₂ (x ² )...(16) r ₁ (x ² )△=r ₀ (1)+r ₁ (1)x ² +r ₂ (1 )x ⁴ ………(17) r ₂ (x ² )△=r ₀ (2)+r ₁ (2)x ² +r ₂ (2)x ⁴ +……(18
) e ₁ (x ² )△=e ₀ (1)+e ₁ (1)x ² +e ₂ (1)x ⁴ +…
...(19) e ₂ (x ² ) = b ₀ (2) + b ₁ (2)x ² + b ₂ (2)x ⁴ +... ... (20).

Similarly, the decoding algorithm is expressed as a polynomial using equation (6) above: A^ (x ² ) = (1 + x ² ) r ₂ (x ² ) + x ² J (x ² ) + A^ ₀ + r ₀ (2) ...(21) becomes. However, A^ (x ² ) = A^ ₀ + A^ ₁ x ² + A^ ₂ x ⁴ +... (22) where A ₀ is the initial value determined by the initial state of decoding flip-flops 506 and 507. .

Using these formulas, when decoding output A(x ² ) is expressed as transmission data A(x ² ), if we consider separately when the delay amount L is zero or an even number and when it is an odd number, A(x ² ) =X ^L {A(x ² )+J(x ² )+A ₀ +b ₀ (2)+1
}+(1+x ² )e ₂ (x ² )+x ² J(x ² )+A^ ₀ +r ₀ (2) (L is zero or even number) (L is zero or even number) X ^L+1 A(x ² ) +X ^L-1 {J(x ² )+b ₀ (1)+1}+(1+x
² ) e ₂ (x ² ) + x ² J (x ² ) + A ₀ + r ₀ (2) (L is an odd number) ...(23) ...(24) Therefore, ignore the delay amount and use T instead of x. _{To represent} the decoded data using x, which _represents the amount of delay in
)e ₂ (X)……(25) A^(X)=XA(X)+b ₀ (1)+A^ ₀ +r ₀ (2)+(1+X
)e ₂ (X)...(25) A(X)+A ₀ +b ₀ (2)+A^ ₀ +r ₀ (2)+(1+X)e ₂ (X
)...(26)

In this way, when using the decoding circuit of one embodiment of the present invention in the FM code, the first bit (X ⁰ term) may be erroneous depending on the initial state of the memory; After that, it can be decoded correctly.

In the above embodiment, the case of FM code was explained, but even with other transmission line codes that convert into 1-bit and 2-bit codes, the result is a difference in the 1st and 2nd bits of the 2-bit encoded output. Even if the present invention is applied to a transmission path code that is dynamically encoded, the same effects as described above can be obtained.

As described above, according to the present invention, since the FM code decoding circuit is configured to perform differential decoding,
Unlike a synchronous decoding circuit, there is no need for a synchronization detection circuit, and there is no need to pay special attention to synchronization. Thereby, it is possible to achieve asynchronous decoding that does not cause decoding errors due to synchronization errors.

[Brief explanation of the drawing]

FIG. 1 is an electrical circuit diagram showing an example of a conventional encoding circuit, and FIG. 2 is a timing chart thereof. FIG. 3 is an electrical circuit diagram showing an example of a conventional decoding circuit, and FIG. 4 shows its timing chart. FIG. 5 is an electric circuit diagram showing an embodiment of a decoding circuit according to an embodiment of the present invention, and FIG. 6 is a timing chart thereof. In the figure, 104, 105, 505, 50
6,507 is a flip-flop, 106,10
7,509 is an AND gate, 109 is an OR gate,
110,510 is an inverter, 108,508 is
Showing EXOR gate.

Claims (1)

[Claims] 1. Transmission in which data is FM-encoded by an encoding circuit into a binary code in which the first half of the T bit cycle is T/2 bit cycle and the second half is T/2 bit cycle, and then transmitted. In a decoding circuit that decodes a data sequence based on a clock pulse with a T/2 bit period, the decoding clock pulse generating means generates a decoding clock pulse with a bit period based on the clock pulse with a T/2 bit period; a first gate means for generating a pulse corresponding to the latter half of the T/2 bit period based on a clock pulse having a /2 bit period and a decoding clock pulse from the decoding clock pulse generating means; a second half bit selection means for selecting a binary code of the second half bit from the received data sequence based on a pulse generated from the second half bit selection means based on a decoding clock pulse generated from the decoding clock pulse generation means; a delay means for delaying the binary code of the selected second half bit by T bit periods; and a binary code of the current second half bit selected by the second half bit selection means and the previous second half outputted from the delay means. a decoding circuit comprising second gate means for decoding the original data based on the binary code of the bits;