JPS5612131A - Synthesizer type receiver - Google Patents

Synthesizer type receiver

Info

Publication number
JPS5612131A
JPS5612131A JP8773979A JP8773979A JPS5612131A JP S5612131 A JPS5612131 A JP S5612131A JP 8773979 A JP8773979 A JP 8773979A JP 8773979 A JP8773979 A JP 8773979A JP S5612131 A JPS5612131 A JP S5612131A
Authority
JP
Japan
Prior art keywords
time
output
latch circuit
circuit
pulse generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8773979A
Other languages
Japanese (ja)
Other versions
JPS644372B2 (en
Inventor
Kiyotake Fukui
Toshiaki Inui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP8773979A priority Critical patent/JPS5612131A/en
Publication of JPS5612131A publication Critical patent/JPS5612131A/en
Publication of JPS644372B2 publication Critical patent/JPS644372B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To vary a reception frequency securely even when the repetitive speed of pulses increases by driving a counter reset periodically with a channel selection pulse and then by supplying its output to a PLL circuit via a latch circuit.
CONSTITUTION: The output of channel selection pulse generator 15 is supplied to up-down counter 21, the output of which is read out by latch circuit 20 at very time T determined by periodic pulse generator 22 and held for time T. Dividing-ratio setting circuit 13 is controlled by the output of latch circuit 20 to keep division ratio N constant for time T and time T is made much longer than the response time of PLL circuit 16, so that PLL circuit 16 will follow up at intervals of time T. Further, counter 21 is reset right after its output is read by latch circuit 20 and in the next time T, pulses generated by pulse generator 15 are securely counted.
COPYRIGHT: (C)1981,JPO&Japio
JP8773979A 1979-07-10 1979-07-10 Synthesizer type receiver Granted JPS5612131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8773979A JPS5612131A (en) 1979-07-10 1979-07-10 Synthesizer type receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8773979A JPS5612131A (en) 1979-07-10 1979-07-10 Synthesizer type receiver

Publications (2)

Publication Number Publication Date
JPS5612131A true JPS5612131A (en) 1981-02-06
JPS644372B2 JPS644372B2 (en) 1989-01-25

Family

ID=13923288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8773979A Granted JPS5612131A (en) 1979-07-10 1979-07-10 Synthesizer type receiver

Country Status (1)

Country Link
JP (1) JPS5612131A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57163846U (en) * 1981-04-08 1982-10-15

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57163846U (en) * 1981-04-08 1982-10-15
JPS6345062Y2 (en) * 1981-04-08 1988-11-22

Also Published As

Publication number Publication date
JPS644372B2 (en) 1989-01-25

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