CN116089937B - All-digital sensor capable of resisting multiple fault injection - Google Patents
All-digital sensor capable of resisting multiple fault injection Download PDFInfo
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- CN116089937B CN116089937B CN202310371761.7A CN202310371761A CN116089937B CN 116089937 B CN116089937 B CN 116089937B CN 202310371761 A CN202310371761 A CN 202310371761A CN 116089937 B CN116089937 B CN 116089937B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/55—Detecting local intrusion or implementing counter-measures
- G06F21/556—Detecting local intrusion or implementing counter-measures involving covert channels, i.e. data leakage between processes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
- Y02T10/00—Road transport of goods or passengers
- Y02T10/10—Internal combustion engine [ICE] based vehicles
- Y02T10/40—Engine management systems
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/50—Systems or methods supporting the power network operation or management, involving a certain degree of interaction with the load-side end user applications
- Y04S10/52—Outage or fault management, e.g. fault detection or location
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Abstract
The invention discloses a full-digital sensor capable of resisting various fault injection, which belongs to the technical field of sensors and comprises a total delay line formed by cascading a plurality of delay units, wherein the total delay line is divided into two delay lines with a length and a length, a signal input end of the long delay line is connected with a clock signal, and a signal output end of the long delay line is connected with a short delay line; the invention designs an extensible all-digital sensor by adopting standard units, can resist attack means such as clock burr application, clock frequency improvement, voltage burr application, power supply voltage reduction, heating, electromagnetic interference and laser injection, and has the characteristics of small area, wide application and the like.
Description
Technical Field
The invention relates to the technical field of sensors, in particular to an all-digital sensor capable of resisting various fault injection.
Background
In the field of information security, fault injection is a common attack means. An attacker applies clock burrs to the chip, so that the clock frequency is improved, voltage burrs are applied, the power supply voltage is reduced, and key paths are invalid due to physical means such as heating, electromagnetic interference, laser injection and the like, so that information leakage is caused. In order to resist such attacks, various sensors are required to be built in the chip to detect such attacks, and analog sensors are limited in that only one or a few attack modes can be detected.
Disclosure of Invention
The present invention is directed to an all-digital sensor capable of resisting various fault injections, so as to solve the problems set forth in the background art.
In order to achieve the above purpose, the present invention provides the following technical solutions:
the total delay line is divided into two long delay lines and one short delay line, the signal input end of the long delay line is connected with a clock signal, and the signal output end of the long delay line is connected with the short delay line.
As a further technical scheme of the invention: the delay unit is a programmable delay unit.
As a further technical scheme of the invention: the delay unit comprises an inverter A1, an exclusive OR gate U2 and an exclusive OR gate U3.
As a further technical scheme of the invention: the input end of the inverter A1 is connected with the programming signal TR and one input end of the exclusive-OR gate U2, the output end of the inverter A1 is connected with one input end of the exclusive-OR gate U1, the other input end of the exclusive-OR gate U1 is connected with the other input end of the exclusive-OR gate U2 and the signal IN, the output end of the exclusive-OR gate U2 is connected with one input end of the exclusive-OR gate U3, the output end of the exclusive-OR gate U1 outputs the signal PASS, the other input end of the exclusive-OR gate U3 is connected with the signal ret, and the output end of the exclusive-OR gate U3 outputs the signal out.
As a further technical scheme of the invention: when the delay unit is the first stage of the long delay line, the signal IN is a clock signal, the signal out is connected with the input end of the short delay line and outputs delay output clocks C to D triggers, the signal ret is the output end of the exclusive OR gate U3 IN the delay unit of the later stage, and the signal PASS is used as the signal IN of the delay unit of the later stage;
when the delay unit is the middle stage of the long delay line, the input signal IN is the signal PASS output by the output end of the exclusive OR gate U1 IN the delay unit of the previous stage, and the signal PASS is used as the signal IN of the delay unit of the next stage; the signal ret is the signal out of the delay unit of the next stage, and the signal out is used as the signal ret of the delay unit of the previous stage;
when the delay unit is the last stage of the long delay line, the input signal IN is the output end of the exclusive OR gate U1 IN the delay unit of the previous stage to output a signal PASS, and the signal PASS is taken as the signal ret of the delay unit of the current stage; the signal out is taken as the signal ret of the delay unit of the upper stage.
As a further technical scheme of the invention: when the delay unit is the first stage of the short delay line, the signal IN is a long delay line output signal, the signal out outputs clock signals D to D triggers, the signal ret is the output end of the exclusive OR gate U3 IN the delay unit of the later stage, and the signal PASS is used as the signal IN of the delay unit of the later stage;
when the delay unit is the middle stage of the short delay line, the input signal IN is the signal PASS output by the output end of the exclusive OR gate U1 IN the delay unit of the previous stage, and the signal PASS is used as the signal IN of the delay unit of the next stage; the signal ret is the signal out of the delay unit of the next stage, and the signal out is used as the signal ret of the delay unit of the previous stage;
when the delay unit is the last stage of the short delay line, the input signal IN is the signal PASS output by the output end of the exclusive OR gate U1 IN the delay unit of the previous stage, and the signal PASS is taken as the signal ret of the delay unit of the current stage; the signal out is taken as the signal ret of the delay unit of the upper stage.
A method for resisting multiple fault injection of an all-digital sensor adopts the all-digital sensor, and the specific method is as follows: firstly, a clock signal clock is sent into a delay line, a programmable delay output clock C is generated by programming signals TR [ n-1:0], the delay output clock C is sent into a short delay line to generate a delay clock D, the delay of the delay output clock C is required to be larger than the delay A of the longest path in a chip, the delay of the delay clock D is smaller than the clock period B of the clock signal clock, the delay output clock C and the delay clock D sample the clock signal clock, and whether the clock signal clock is attacked or not is judged according to the sampling result.
Compared with the prior art, the invention has the beneficial effects that: the invention adopts standard units to design an extensible all-digital sensor, can resist the application of clock burrs, improve the clock frequency, apply voltage burrs, reduce the power supply voltage, heat, electromagnetic interference and laser injection, and has the characteristics of small area, wide application and the like.
Drawings
Fig. 1 is a schematic diagram of a structure of a delay unit;
fig. 2 is a schematic diagram of the overall structure of the system of the present invention.
Fig. 3 is a waveform diagram of a clock signal.
Description of the embodiments
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In embodiment 1, referring to fig. 1-3, an all-digital sensor capable of resisting multiple fault injection includes a total delay line formed by cascade connection of multiple delay units, wherein the total delay line is divided into two delay lines with a length, a signal input end of the long delay line is connected with a clock signal, and a signal output end of the long delay line is connected with a short delay line.
Wherein the delay unit is a programmable delay unit.
As shown in fig. 1, the delay unit includes an inverter A1, an exclusive or gate U2, and an exclusive or gate U3. The input end of the inverter A1 is connected with the programming signal TR and one input end of the exclusive-OR gate U2, the output end of the inverter A1 is connected with one input end of the exclusive-OR gate U1, the other input end of the exclusive-OR gate U1 is connected with the other input end of the exclusive-OR gate U2 and the signal IN, the output end of the exclusive-OR gate U2 is connected with one input end of the exclusive-OR gate U3, the output end of the exclusive-OR gate U1 outputs the signal PASS, the other input end of the exclusive-OR gate U3 is connected with the signal ret, and the output end of the exclusive-OR gate U3 outputs the signal out.
As shown IN fig. 2, when the delay unit is the first stage of the long delay line, the signal IN is a clock signal, the signal out is connected to the input end of the short delay line and outputs delayed output clocks C to D flip-flops, the signal ret is the output end of the exclusive or gate U3 IN the delay unit of the subsequent stage, and the signal PASS is the signal IN of the delay unit of the subsequent stage;
when the delay unit is the middle stage of the long delay line, the input signal IN is the signal PASS output by the output end of the exclusive OR gate U1 IN the delay unit of the previous stage, and the signal PASS is used as the signal IN of the delay unit of the next stage; the signal ret is the signal out of the delay unit of the next stage, and the signal out is used as the signal ret of the delay unit of the previous stage;
when the delay unit is the last stage of the long delay line, the input signal IN is the output end of the exclusive OR gate U1 IN the delay unit of the previous stage to output a signal PASS, and the signal PASS is taken as the signal ret of the delay unit of the current stage; the signal out is taken as the signal ret of the delay unit of the upper stage.
When the delay unit is the first stage of the short delay line, the signal IN is a long delay line output signal, the signal out outputs clock signals D to D triggers, the signal ret is the output end of the exclusive OR gate U3 IN the delay unit of the later stage, and the signal PASS is used as the signal IN of the delay unit of the later stage;
when the delay unit is the middle stage of the short delay line, the input signal IN is the signal PASS output by the output end of the exclusive OR gate U1 IN the delay unit of the previous stage, and the signal PASS is used as the signal IN of the delay unit of the next stage; the signal ret is the signal out of the delay unit of the next stage, and the signal out is used as the signal ret of the delay unit of the previous stage;
when the delay unit is the last stage of the short delay line, the input signal IN is the signal PASS output by the output end of the exclusive OR gate U1 IN the delay unit of the previous stage, and the signal PASS is taken as the signal ret of the delay unit of the current stage; the signal out is taken as the signal ret of the delay unit of the upper stage.
In embodiment 2, on the basis of embodiment 1, the invention also discloses a method for resisting various fault injection of the all-digital sensor, wherein the all-digital sensor in embodiment 1 is adopted, and the specific method is as follows: firstly, a clock signal clock is sent into a delay line, a programmable delay output clock C is generated by programming signals TR [ n-1:0], the delay output clock C is sent into a short delay line to generate a delay clock D, the delay of the delay output clock C is required to be larger than the delay A of the longest path in a chip, the delay of the delay clock D is smaller than the clock period B of the clock signal clock, the delay output clock C and the delay clock D sample the clock signal clock, and whether the clock signal clock is attacked or not is judged according to the sampling result.
The working principle is as follows: first, by programming TR [ n-1:0] in FIG. 2, a programmable delay output clock C is generated, which is then fed into a short delay line to generate delay clock D. Ensuring that the delay of C is greater than N times the delay a of the longest path in the chip and the delay of D is less than N times the clock period B of the clock. And the delay clocks C and D sample the clock and judge whether the clock is attacked or not according to the sampling result.
As shown in fig. 3, the horizontal axis arrow represents the time axis, and the bold scale on the upper side represents time periods … Tj-1, tj, tj+1, tj+2 …, assuming that the clock period is B and the critical path delay of the chip is a. An attacker applies clock burrs, improves clock frequency, applies voltage burrs, reduces power supply voltage, heats, electromagnetic interference and injects laser into the attack means, so that the establishment (setup) time of a critical path A is illegal, and a circuit is invalid, thereby obtaining confidential information.
The basic delay unit j0 is constructed as shown in fig. 1, and two delay lines, one long (upper) and one short (lower), are constructed as shown in fig. 2. The long delay line may be programmed (one-time-thermally encoded) by TR and the short delay line may employ a fixed number of steps delay or a programmable delay. The difference between critical path ase:Sub>A and period B (B-ase:Sub>A) is referred to as the margin, which depends on the complexity of the actual circuit, and if the logic is complex, the margin tends to be small, at which time the minimum delay xor gate needs to be selected to improve the accuracy of the delay cell.
According to practical circumstances, TR is programmed to ensure that the delay of delay output C is greater than a and the delay of delay output D is less than clock period B. Delay clocks C and D are respectively sent into two D triggers to sample the clock. From fig. 3, it can be seen that the C, D samples are all 0. Once the chip is subjected to the attacks of clock glitch application, clock frequency is increased, voltage glitch application, power supply voltage reduction, heating, electromagnetic interference and laser injection. The state that both the C and the D sample to 0 is broken immediately, so that attack can be detected and alarm can be given.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (3)
1. The all-digital sensor capable of resisting various fault injection is characterized by comprising a total delay line formed by cascading a plurality of delay units, wherein the total delay line is divided into two delay lines with a length and a short length, the signal input end of the long delay line is connected with a clock signal clock, and the signal output end of the long delay line is connected with a short delay line;
the delay unit comprises an inverter A1, an exclusive OR gate U2 and an exclusive OR gate U3; the input end of the inverter A1 is connected with a programming signal TR and one input end of the exclusive-OR gate U2, the output end of the inverter A1 is connected with one input end of the exclusive-OR gate U1, the other input end of the exclusive-OR gate U1 is connected with the other input end of the exclusive-OR gate U2 and the signal IN, the output end of the exclusive-OR gate U2 is connected with one input end of the exclusive-OR gate U3, the output end of the exclusive-OR gate U1 outputs a signal PASS, the other input end of the exclusive-OR gate U3 is connected with a signal ret, and the output end of the exclusive-OR gate U3 outputs a signal out;
when the delay unit is the first stage of the long delay line, the signal IN is a clock signal, the signal out is connected with the input end of the short delay line and outputs delay output clocks C to D triggers, the signal ret is the output end of the exclusive OR gate U3 IN the delay unit of the later stage, and the signal PASS is used as the signal IN of the delay unit of the later stage;
when the delay unit is the middle stage of the long delay line, the input signal IN is the signal PASS output by the output end of the exclusive OR gate U1 IN the delay unit of the previous stage, and the signal PASS is used as the signal IN of the delay unit of the next stage; the signal ret is the signal out of the delay unit of the next stage, and the signal out is used as the signal ret of the delay unit of the previous stage;
when the delay unit is the last stage of the long delay line, the input signal IN is the output end of the exclusive OR gate U1 IN the delay unit of the previous stage to output a signal PASS, and the signal PASS is taken as the signal ret of the delay unit of the current stage; the signal out is taken as a signal ret of a delay unit at the upper stage;
when the delay unit is the first stage of the short delay line, the signal IN is a long delay line output signal, the signal out outputs clock signals D to D triggers, the signal ret is the output end of the exclusive OR gate U3 IN the delay unit of the later stage, and the signal PASS is used as the signal IN of the delay unit of the later stage;
when the delay unit is the middle stage of the short delay line, the input signal IN is the signal PASS output by the output end of the exclusive OR gate U1 IN the delay unit of the previous stage, and the signal PASS is used as the signal IN of the delay unit of the next stage; the signal ret is the signal out of the delay unit of the next stage, and the signal out is used as the signal ret of the delay unit of the previous stage;
when the delay unit is the last stage of the short delay line, the input signal IN is the signal PASS output by the output end of the exclusive OR gate U1 IN the delay unit of the previous stage, and the signal PASS is taken as the signal ret of the delay unit of the current stage; the signal out is taken as the signal ret of the delay unit of the upper stage.
2. An all-digital sensor resistant to multiple fault injection as claimed in claim 1, wherein said delay unit is a programmable delay unit.
3. A method for resisting multiple fault injection of an all-digital sensor, which is characterized in that the all-digital sensor as claimed in any one of claims 1-2 is adopted, and the specific method is as follows: firstly, a clock signal clock is sent into a delay line, a programmable delay output clock C is generated by programming signals TR [ n-1:0], the delay output clock C is sent into a short delay line to generate a delay clock D, the delay of the delay output clock C is required to be larger than the delay A of the longest path in a chip, the delay of the delay clock D is smaller than the clock period B of the clock signal clock, the delay output clock C and the delay clock D sample the clock signal clock, and whether the clock signal clock is attacked or not is judged according to the sampling result.
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| CN105932998A (en) * | 2016-04-18 | 2016-09-07 | 宁波大学 | Glitch-type PUF circuit employing delay tree structure |
| CN208723865U (en) * | 2018-09-13 | 2019-04-09 | 长江存储科技有限责任公司 | A kind of duty-ratio calibrating circuit |
| CN109831206B (en) * | 2019-02-13 | 2023-06-27 | 芯原微电子(上海)股份有限公司 | Delay locked loop and delay locking method |
| CN112511135A (en) * | 2020-12-14 | 2021-03-16 | 中国科学院微电子研究所 | Adjustable duty ratio circuit |
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