CN109558111B

CN109558111B - True random number generating device based on metastable state characteristic of D trigger

Info

Publication number: CN109558111B
Application number: CN201811203996.0A
Authority: CN
Inventors: 林桐; 杨柱; 郑伟; 王茵; 戴春泉
Original assignee: Beijing Institute Of Technology Leike Aerospace Information Technology Co ltd
Current assignee: Beijing Institute Of Technology Leike Aerospace Information Technology Co ltd
Priority date: 2018-10-16
Filing date: 2018-10-16
Publication date: 2023-09-29
Anticipated expiration: 2038-10-16
Also published as: CN109558111A

Abstract

The invention provides a device and a method for generating true random numbers based on metastable state characteristics of a D trigger, which can generate the true random numbers in an FPGA or a chip by only relying on a digital circuit. The invention relates to a true random number generating device based on metastable state characteristics of a D trigger, which comprises a data input module, a combination logic module and a synchronous output module, wherein the data input module comprises two groups of data selectors and four groups of registers, and each two groups of registers are correspondingly connected with one group of data selectors; the combinational logic module comprises a shifter, a selector, an adder and an exclusive-OR gate, wherein the shifter, the selector, the adder and the exclusive-OR gate are sequentially connected.

Description

True random number generating device based on metastable state characteristic of D trigger

Technical Field

The invention belongs to the technical field of digital circuits, and relates to a true random number generating device based on metastable state characteristics of a D trigger.

Background

The random sequence properties are as follows: (1) Appears to be random, i.e. it can pass all the correct randomness checks that can be found; (2) This sequence is unpredictable, that is, even given the algorithm or hardware design that produced the sequence and all knowledge of the sequence that has been produced before, it is not possible to predict by calculation what the next random bit is; (3) This sequence cannot be repeated even if you operate twice with exactly the same input sequence generating means under exactly the same operating conditions (same place, same temperature, etc.), two completely different, non-correlated random sequences will be obtained.

Metastable is defined as the output of a register may enter metastable when a change in data does not meet the set-up or hold time requirements of the clock. Metastable means that the output signal cannot enter a known state within a predetermined time, that is, the propagation delay of the device exceeds a nominal value. In the metastable state, the output of the register remains between a high level and a low level for a period of time, that is, after a propagation delay time, the register output signal is at an intermediate level. Once the circuit enters a metastable state, the time to stay in the metastable state will be unpredictable. After the occurrence of the metastable state, even if the final output is stabilized, the designer cannot be sure that the logic value of the output is necessarily correct. During the change of the output signal from metastable to steady state, the output signal may be free from illegal logic level values for a long period of time, and oscillations may also occur.

The D flip-flop is a sequential circuit composed of level devices like D latches. A typical rising edge valid D flip-flop model consisting of D latches is analyzed. When the clock input port is maintained at a high level, the input terminal inputs a value D0 at a certain time. This value enters from the input nand gate, there is a delay in the device, and there may be an inconsistency between the signal fed back to one input of the nand gate and the signal at the other input, so that during the entire set-up of the D latch, there is an "unstable phase" of the voltage output from the output of the first stage, called the set-up time, the "length" of this unstable phase being related to the device propagation delay, and the input level, the initial level of the output of the first stage (assuming that the clock level is always unchanged). Note that the start position of this period is at the point where the input starts to be valid. Since a time period has elapsed after the input of the input terminal, the output terminal of the first stage starts to "oscillate". Starting from the rising edge of the clock port, and ending at the point before the window time when the input must be valid, this time is the setup time of the D flip-flop. Starting from the rising edge of the clock port, and ending at a point after the window time when the input must be valid, this time is the hold time of the D flip-flop. The time from the rising edge of the clock port to the stable end of the output end is the propagation delay time of the D trigger.

The D flip-flop produces metastability analysis as follows: any level anomaly during the sampling window time may cause sampling anomalies, which is the most fundamental cause of metastability. It is assumed that when the clock of the first stage of the D flip-flop is turned off, the different input levels at the input end are "frozen" to an initial value, and if this initial value is exactly the intermediate level, the output end of the first stage latch will take a longer time to reach the due level height, and the combined effect of the mutual feedback inputs will eventually lengthen the set-up time of the whole latch. In addition, since the system is subject to various noise at any time, adding noise results in the final level being independent of the input.

Metastability analysis of D flip-flops within the same clock domain: it is assumed that there is a very long and complex chain of combinational logic devices between two adjacent D flip-flops. Therefore, the data from the previous stage D flip-flop needs to be stabilized at the input end of the next stage D flip-flop after a long time. This time is even close to the clock period and the signal is stable after the start of the sampling window, so that the D flip-flop first stage does not have enough time to correctly set the level, resulting in the occurrence of metastable states. This situation is called a setup time violation. Alternatively, if the rising edge of the first cycle, the data D0 from the previous stage flip-flop reaches the next stage. There is a rising edge in the second cycle, and the data D1 from the previous stage flip-flop passes through a very short path to the next stage. If this transmission time is less than the hold time, D1 will in turn destroy the sample when the last D0 has not completely ended the sample. Thus creating a hold time violation.

Disclosure of Invention

The invention aims to provide a device and a method for generating a true random number based on metastable state characteristics of a D trigger, which can generate the true random number in an FPGA or a chip by only relying on a digital circuit.

The invention is realized by the following technical scheme:

the true random number generating device based on the metastable state characteristic of the D trigger comprises a data input module, a combinational logic module and a synchronous output module, wherein the data input module comprises two groups of data selectors and four groups of registers, and each two groups of registers are correspondingly connected with one group of data selectors; the combinational logic module comprises a shifter, a selector, an adder and an exclusive-OR gate, wherein the shifter, the selector, the adder and the exclusive-OR gate are sequentially connected in sequence;

the register is used for storing a register value conforming to a metastable state generating condition;

the data selector is used for selecting different registers as output values, one output is connected with the input of the shifter in the combinational logic module, and the other output is connected with the control input of the signal selector in the combinational logic module;

the shifter is used for multiplying the input value by 2 to the power of n and outputting the result to the signal selector;

the signal selector is used for selecting the output result of the shifter or selecting all 0 outputs, and the output of the signal selector is connected with the input of the adder;

the adder is used for adding the outputs of the signal selectors, and the output of the adder is connected with the input of the exclusive-OR gate;

the exclusive-or gate is used for converting the multi-bit signal output by the adder into a single-bit signal meeting the metastable state generation condition and outputting the single-bit signal to the synchronous output module;

the synchronous output module is used for locking the signal which is output by the exclusive-OR gate and meets the metastable state generation condition to stable 0 or 1, and finally obtaining the random number.

The invention has the beneficial effects that:

the invention realizes the generation of the true random number by utilizing the metastable state characteristic of the D trigger, and designs a circuit which can ensure that each clock period can enter the metastable state. Multiplication functions are implemented using combinational logic (shifters and adders) that is relatively complex and long-path; meanwhile, the output result is exclusive-ored according to the bits, so that the length of a combined logic path is increased, and the condition that the output exclusive-ored result enters the D trigger A to generate metastable state can be met as long as at least one path time sequence violation exists in exclusive-ored input. After entering the metastable state, the state is restored to the steady state 1 or 0 randomly according to the characteristic of the metastable state, so that the true random number is realized by the full digital logic, and the true random number can be realized on a chip which cannot integrate an analog device, such as an FPGA.

Drawings

Fig. 1 is a schematic diagram of a true random number generating device based on metastable state characteristics of a D flip-flop.

Detailed Description

As shown in fig. 1, the true random number generating device based on metastable state characteristics of the D flip-flop of the present invention includes a data input module, a combinational logic module and a synchronous output module, wherein the data input module includes two sets of data selectors (selector 0, selector 1) and four sets of registers (register 0, register 1, register 2, register 3), each two sets of registers corresponds to one set of data selectors, and the two-stage synchronous circuit is composed of a 32-bit two-input multiplier implemented by shift addition, a 64-bit bitwise exclusive-or circuit, a D flip-flop a, a D flip-flop B and a D flip-flop C. The specific implementation process of random number generation is as follows:

1. by checking a time sequence analysis report generated after circuit synthesis, the input of the 32-bit multiplier consists of two groups of register outputs, and the condition that the setup time violation is generated on the path of a D trigger (D trigger A) of which register output reaches the exclusive OR result input is confirmed;

2. the circuit of the true random number generating device starts to work, the register value obtained in the step 1 is used as the input value of the data input module, and the output value selected by the data selector is used as the input of the combinational logic circuit. Since the result after 64'H AAAA_AAAA_AAAA_AAAA is 0 after bitwise exclusive or, the result after 64' h1555_5555_5555_5555 is 1 after bitwise exclusive or, the length of 64 combinational logic paths is not consistent, and there is a setup time violation path, it can be ensured that the input port D of the D flip-flop a continuously turns 0 and 1 and may be at a level between 0 and 1, i.e., in the clock rising edge window (within the setup time and the hold time) of the D flip-flop a, the input port D is not stable, the condition of generating metastable state is satisfied, the output of the D flip-flop a enters metastable state, i.e., the combinational logic module outputs a metastable state signal. The output of the combination logic module enters the next-stage synchronous output module, after two-stage synchronous processing of the D trigger B and the D trigger C, the final output enters a steady state, and signals entering the steady state are interfered by thermal noise and electric noise in a circuit, and the signals can be 0 or 1, so that the output of the D trigger C, namely the output of the synchronous output module, is a true random number.

Assuming that there is a setup time violation for bit 10 of multiplier X to D flip-flop a, register 0X register 2=64' haaaa aaaa; register 1 x register 3=64' h1555_5555_5555_5555; bit 10 of register 0 is 0; bit 10 of register 1 is 1. Since 64'H AAAA_AAAA_AAAA_AAAA is 0 after bit exclusive or, 64' h1555_5555_5555_5555 is 1 after bit exclusive or, 64 combinational logic paths are not long and short, and there is a setup time violation path, that is, the input port D of the D flip-flop a is enabled to continuously flip between 0 and 1 and may be at a level between 0 and 1, in the clock rising edge window of the D flip-flop a, the input port D is not stable, and the condition of generating metastable state is satisfied. Therefore, the output port Q of the D trigger A cannot reach a steady state in a decision time, but enters a metastable state;

3. the output of the D trigger A is acquired through the D trigger B and the D trigger C, no combinational logic exists between three stages of registers, the metastable state propagation is blocked, the metastable state signal is changed into a steady state signal, the steady state signal is interfered by thermal noise and electric noise in a circuit, the steady state signal can be 0 or 1, and the output of the D trigger C is ensured to be a true random number.

Claims

1. The true random number generating device based on the metastable state characteristic of the D trigger is characterized by comprising a data input module, a combination logic module and a synchronous output module, wherein the data input module comprises two groups of data selectors and four groups of registers, and each two groups of registers are correspondingly connected with one group of data selectors; the combinational logic module comprises a shifter, a selector, an adder and an exclusive-OR gate, wherein the shifter, the selector, the adder and the exclusive-OR gate are sequentially connected in sequence;