CN110071803B - True random number generator of pure digital circuit - Google Patents
True random number generator of pure digital circuit Download PDFInfo
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- CN110071803B CN110071803B CN201910368663.1A CN201910368663A CN110071803B CN 110071803 B CN110071803 B CN 110071803B CN 201910368663 A CN201910368663 A CN 201910368663A CN 110071803 B CN110071803 B CN 110071803B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0869—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving random numbers or seeds
Abstract
The invention discloses a pure digital circuit true random number generator, which comprises an entropy source circuit, a sampling circuit and an output register circuit, wherein the sampling circuit is connected with the entropy source circuit; the generator further comprises a post-processing circuit, the post-processing circuit is arranged between the sampling circuit and the output register circuit and respectively connected with the sampling circuit and the output register circuit, the post-processing circuit comprises a linear feedback shift register connected with the sampling circuit, a detection circuit connected with the linear feedback shift register and a random extraction circuit connected with the detection circuit, and the output register circuit is connected with the random extraction circuit to latch the output of the random extraction circuit. The advantages are that: the invention has the characteristics of simple circuit structure, easy realization, higher random number quality, uniform distribution, unpredictability, low power consumption and attack resistance, and has strong engineering reference and application values.
Description
Technical Field
The invention relates to the field of security of cryptographic chips, in particular to a true random number generator with a pure digital circuit.
Background
The smart card is one of the most widely used cryptographic devices of the cryptographic chip, and in order to ensure the security of the smart card, a random number is required to generate an unpredictable key. The random number has two generation modes, one is a pseudo random number generation mode, and the other is a true random number generation mode. The pseudo-random number generator starts from an initial state called 'seed', generates random numbers through a determined algorithm, and the output sequence has periodicity, so that the pseudo-random number generator is easy to attack and has low security. True random number generators derive from random physical processes such as thermal noise, cosmic noise, radioactive decay, etc. of the circuit.
The typical true random number generator comprises resistance thermal noise, oscillator sampling, discrete chaos and the like, and considering that the amplitude of the resistance thermal noise is small, amplification is required by means of a high-gain operational amplifier, but the random characteristic of the random number is poor due to limited bandwidth and imbalance of operational amplifier, a discrete chaos switch network circuit is too complex, the power consumption is high, and the design requirement of low power consumption of the smart card cannot be met. Moreover, the smart card standard puts higher requirements on the random source types and the quality of random numbers, requires a plurality of random sources, is uniform in distribution and independent in sequence, and can resist external physical attacks including side channel attacks.
Disclosure of Invention
It is an object of the present invention to provide a true random number generator for pure digital circuits that solves the aforementioned problems of the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a pure digital circuit true random number generator comprises an entropy source circuit, a sampling circuit and an output register circuit, wherein the sampling circuit is connected with the entropy source circuit; the generator further comprises a post-processing circuit, the post-processing circuit is arranged between the sampling circuit and the output register circuit and respectively connected with the sampling circuit and the output register circuit, the post-processing circuit comprises a linear feedback shift register connected with the sampling circuit, a detection circuit connected with the linear feedback shift register and a random extraction circuit connected with the detection circuit, and the output register circuit is connected with the random extraction circuit to latch the output of the random extraction circuit.
Preferably, the control circuit is connected to the sampling circuit, the linear feedback shift register, the detection circuit, the random access circuit, and the output register circuit, respectively.
Preferably, the entropy source circuit is connected to the sampling circuit, and the sampling circuit uses a low-frequency sampling clock as a clock signal for triggering the D end of the sampling circuit at a rising edge; the output signal of the entropy source circuit is used as a data input signal of a D end of the sampling circuit, and is sampled at the rising edge of the sampling clock pulse, so that a true random number bit stream is obtained at a Q end of the sampling circuit.
Preferably, the entropy source circuit comprises a plurality of random source circuits, namely a first random source circuit based on a metastable state, a second random source circuit based on an even ring collapse time and a third random source circuit based on ring oscillation jitter, and each random source circuit can provide a data input signal to the D end of the sampling circuit.
Preferably, the first random source circuit comprises M SR latch units, the SR latch units are arranged in parallel, and perform an exclusive or operation, and an operation result is output from the entropy source circuit; m is more than or equal to 128.
Preferably, the second random source circuit comprises N inverters and two exclusive or gates which are sequentially connected end to end, and the two exclusive or gates are spaced by N/2 inverters; and N is an even number.
Preferably, the two exclusive or gates are a first exclusive or gate and a second exclusive or gate, respectively, and the second random source circuit has two signal transmission paths, a first signal transmission path and a second signal transmission path, respectively; the first exclusive or gate allows only the first signal transmission path to pass through, and the second exclusive or gate allows only the second transmission path to pass through.
Preferably, the third random source circuit comprises a plurality of ring oscillators, each ring oscillator is composed of an odd number of inverters, and an and gate is arranged in each ring oscillator; the AND gates and the inverters in the same ring oscillator are sequentially connected end to end, the output end of the inverter at the most downstream in the signal transmission direction in the ring oscillator is connected with the input end of the AND gate, and the output end of the AND gate is connected with the input end of the inverter at the most upstream; and connecting the output ends of the ring oscillators with different lengths with the same third XOR gate in pairs for XOR processing, and then connecting the output ends of the third XOR gates with the fourth XOR gate.
Preferably, the linear feedback shift register sends the random number sequence output by the linear feedback shift register to the detection circuit, the random number sequence takes (8m) bits as a unit, and m is the bit width of the random number sequence.
Preferably, the generator further comprises a random extractor circuit, and the random extractor circuit is connected to the detection circuit and is configured to extract the random number sequence sent to the detection circuit to obtain an mbit random number.
The invention has the beneficial effects that: 1. the invention has the characteristics of simple circuit structure, easy realization, higher random number quality, uniform distribution, unpredictability, low power consumption and attack resistance, and has strong engineering reference and application values. 2. The design of the invention not only can be used as a soft IP of the chip of the intelligent card for system calling to meet the requirement of the system on the random number in the operation process, but also can be used as the scheme reference of the design of the true random number in other chip development or FPGA development.
Drawings
FIG. 1 is a block diagram of the overall circuit of a true random number generator in an embodiment of the present invention;
FIG. 2 is a circuit diagram of a metastability-based entropy source according to an embodiment of the present invention;
FIG. 3 is a two-stage SR latch with 4 XOR gates in an embodiment of the present invention;
FIG. 4 is a circuit diagram of an entropy source based on even ring collapse time in an embodiment of the present invention;
FIG. 5 is a schematic diagram of an even number of crash rings in an embodiment of the invention;
FIG. 6 is a circuit diagram of an entropy source based on ring oscillator jitter according to an embodiment of the present invention;
FIG. 7 is a 6-tap 16-bit linear feedback shift register according to an embodiment of the present invention;
FIG. 8 is a flow chart of a random extractor circuit algorithm in an embodiment of the present invention;
FIG. 9 is a schematic diagram of the remote location of a true random number generator in an embodiment of the present invention;
FIG. 10 is a flow diagram of the operation of a true random number generator in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
As shown in FIG. 1, the present invention provides a true random number generator with pure digital circuits, which comprises an entropy source circuit, a sampling circuit and an output register circuit, wherein the sampling circuit is connected with the entropy source circuit; the generator further comprises a post-processing circuit, the post-processing circuit is arranged between the sampling circuit and the output register circuit and respectively connected with the sampling circuit and the output register circuit, the post-processing circuit comprises a linear feedback shift register connected with the sampling circuit, a detection circuit connected with the linear feedback shift register and a random extraction circuit connected with the detection circuit, and the output register circuit is connected with the random extraction circuit to latch the output of the random extraction circuit.
In this embodiment, the control circuit is connected to the sampling circuit, the linear feedback shift register, the detection circuit, the random access circuit, and the output register circuit, respectively.
In this embodiment, the entropy source circuit is connected to the sampling circuit, and the sampling circuit uses a low-frequency sampling clock as a clock signal for triggering a D end of the sampling circuit at a rising edge; the output signal of the entropy source circuit is used as a data input signal at the D end of a sampling circuit (trigger), the sampling circuit is the trigger, and the sampling circuit samples the data input signal at the rising edge of a sampling clock pulse so as to obtain a true random number bit stream at the Q end of the sampling circuit.
In this embodiment, the entropy source circuit is responsible for generating random numbers, and is the most important component in the random number generator; the sampling circuit is responsible for quantizing the randomness in the entropy source circuit into a random binary sequence; the post-processing circuit aims at processing the binary sequence output by the sampling circuit, hiding or eliminating the bias introduced in the entropy source circuit or the sampling circuit, improving the statistical property of random numbers and achieving the purpose of resisting attack; the output register circuit is responsible for latching the true random number output by the post-processing circuit and outputting the true random number to the outside of the chip or other modules of the chip for use; the control circuit is responsible for generating control signals related to the operation of the random number generator, and comprises low power consumption control, flow control and the like.
In this embodiment, the entropy source circuit includes a plurality of random source circuits, which are respectively a first random source circuit based on a metastable state, a second random source circuit based on an even ring collapse time, and a third random source circuit based on ring oscillation jitter, and each random source circuit can provide a data input signal to the D terminal of the sampling circuit.
Example one
As shown in fig. 2 to 6, the present embodiment explains in detail various entropy source circuits: as shown in fig. 2, the first random source circuit includes M SR latch units, and the SR latch units are arranged in parallel and perform an exclusive or operation, and the operation result is output from the entropy source circuit; m is more than or equal to 128. That is to say, based on the random source circuit structure of metastable state, m SR latch units are used to output the exclusive or result as the output of entropy source, fig. 3 is a structural diagram of each SR latch unit, which includes 4 exclusive or gates, and when S ═ R ═ 1, the latch is in the indeterminate state of neither 1 nor 0; the specific output logic value is determined by the instantaneous level of the NAND gate and the absolute and relative value of internal noise, tests show that the larger the ratio of the sampling clock to the oscillation clock is, the stronger the randomness is, the less the number of the SR latch units is easy to select, otherwise, the randomness test cannot be passed, the increased number of the SR latch units can effectively improve the randomness of generating random numbers, and generally m > 128 can meet the requirements.
In this embodiment, as shown in fig. 4 to 5, the second random source circuit includes N inverters and two exclusive or gates connected end to end in sequence, and N/2 inverters are spaced between the two exclusive or gates; and N is an even number. The two exclusive-or gates are respectively a first exclusive-or gate and a second exclusive-or gate, and the second random source circuit is provided with two signal transmission paths which are respectively a first signal transmission path and a second signal transmission path; the first exclusive or gate allows only the first signal transmission path to pass through, and the second exclusive or gate allows only the second transmission path to pass through.
In this embodiment, as shown in fig. 5, the second random source circuit is a loop formed by an even number of inverters and two exclusive or gates, and is referred to as an "even collapse ring". In the loop, there are two signal transmission paths including a first transmission path and a second transmission path. Represented in fig. 5 using "… …" and "- - -" respectively. The paths that the rising and falling edges of the same inverter input travel in the loop are different. The same rising edge is input at the beginning of different paths (port A and port B) of the loop at the same time, and after a period of time, the two edges meet, and the loop is in a stable state. The time from input to stabilization of the transmission edge is called the collapse time. The propagation delay for each path is the sum of each transistor parameter and noise. The randomness of the collapse time is determined by the randomness of the noise of each inverter. The collapse time can be a random source for a true random number generator.
In this embodiment, as shown in fig. 4, the even crash loop has 2n stages of inverters, a frequency-divided clock sckxdiv (x is 4, 8..) of the sampling clock sclk is used as an input pulse, an output of the inverter Bn is used as a counting pulse, the counter cnt1 starts counting during the period when sclkxdiv is high, and the counter cnt2 starts counting during the period when sclkxdiv is low. The 0 th bit and the 1 st bit of the counting value are subjected to XOR operation to be output as the output of the entropy source, and the XOR operation is carried out for improving the randomness of the random number. In order to count the breakdown time as accurately as possible, if sckxdiv is divided by four, the sampling circuit should acquire a random number of 1bit every other clock cycle. If the pulse input by the even number breakdown ring is 8 times division of the sampling clock, the sampling circuit should acquire a random number of 1bit every 3 clock periods, and so on.
In this embodiment, as shown in fig. 6, the third random source circuit includes a plurality of ring oscillators, each ring oscillator is composed of an odd number of inverters, and an and gate is disposed in each ring oscillator; the AND gates and the inverters in the same ring oscillator are sequentially connected end to end, the output end of the inverter at the most downstream in the signal transmission direction in the ring oscillator is connected with the input end of the AND gate, and the output end of the AND gate is connected with the input end of the inverter at the most upstream; and connecting the output ends of the ring oscillators with different lengths with the same third XOR gate in pairs for XOR processing, and then connecting the output ends of the third XOR gates with the fourth XOR gate.
In this embodiment, each ring oscillator of the entropy source circuit diagram based on the ring oscillator jitter is composed of a plurality of odd-numbered inverters, the output of the last inverter is fed back to the input of the first inverter, the delay time of the inverters changes due to the influence of thermal noise, shot noise, low-frequency noise and the like in an oscillation link, and further the oscillation frequency changes, and the uncertainty of the jitter frequency can be used as the source of the random number.
In this embodiment, the timing jitter of one oscillation ring cannot be used as a high-quality entropy source, and it is necessary to perform xor by using a plurality of ring oscillators to improve the randomness. Meanwhile, when the lengths of different ring oscillations are prime numbers, the randomness of the entropy source is better. The reason is that when the lengths of the two ring oscillator chains are the same, the oscillation frequencies are similar, the hopping regions are greatly overlapped, when the two oscillators hop simultaneously, the entropy in the time sequence jitter is wasted, in order to reduce the overlapping as much as possible, the two oscillators with different lengths should be selected for exclusive-or, considering that when the lengths of the two oscillators are prime numbers, the oscillation frequencies are also prime numbers, and in the period of the greatest common multiple of the two oscillators, the hopping regions do not overlap, so that the waste of the entropy is reduced to the greatest extent. And meanwhile, an AND gate is added in the ring oscillator, and when the circuit does not need to work, the clock is turned off, so that the requirement of low-power-consumption design is met. In fig. 6, the ring length is taken as: 3. 5,7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59.
Example two
As shown in fig. 7 to fig. 10, the linear feedback shift register sends the random number sequence output by the linear feedback shift register to the detection circuit, where the random number sequence uses (8m) bits as a unit, and m is the bit width of the random number sequence; the detection circuit detects a random number sequence.
In this embodiment, the generator further includes a random extractor circuit, and the random extractor circuit is connected to the detection circuit and configured to extract the random number sequence sent to the detection circuit to obtain an mbit random number.
In the present embodiment, as shown in FIG. 7, the feedback relationship of the circuit formed by the 6-tap 16-bit Linear Feedback Shift Register (LFSR) and the XOR gate is 1 bit-Reg [0] of Reg [15] A input; reg [5] ^ Reg [15] - > Reg [5 ]; reg [12] ^ Reg [15] - > Reg [12 ]. And 6bit values of 1,4,5,7,8 and 9 are extracted and are subjected to logic operation to be used as the value of the random number of the 1bit after mapping. Firstly, filling the 16-bit LSFR with a true random number as a seed of the LSFR, wherein the random number sequence output by the LSFR is invalid, and the random number sequence output by the LFSR is considered valid after the 16 bits of the LSFR are completely filled.
In this embodiment, as shown in fig. 8, it is a flow chart of an algorithm of a random extractor circuit; the random number is automatically discarded without passing through a detection circuit; the (8m) bit random number that passes through the detection circuit is then fed to a random extractor circuit for further processing. The random extractor circuit is designed for preventing attacks, and randomly extracts the random number of (8m) bits to obtain the random number of mbit. The invention constructs a random extractor circuit by using the Toeplitz matrix, and the mathematical relationship proves that the randomness of an entropy source can be well extracted to a certain degree and the unpredictability of output can be ensured under the conditions of changing physical environment and attacks existing in the environment. In fig. 8, a is input 256-bit data, B is output 32-bit data, and PI is a constant value of 288 bits.
In this embodiment, the random extractor circuit is not a module that must not be lost for the design of the true random number generator, and although the addition of the circuit achieves the purpose of resisting some intrusion and non-intrusion attacks including side channels to some extent, the extraction of mbit from (8m) bitt random numbers as the final random number sequence output greatly reduces the efficiency of generating random numbers, and the area and power consumption of the whole circuit increase, so the circuit should be selected and used or discarded in combination with the actual application.
EXAMPLE III
As shown in FIGS. 9 and 10, a schematic diagram and a control flow diagram of a true random number generator of the present invention are presented; the true random number generator in the invention can be used as a soft IP of a smart card chip for system calling so as to meet the requirement of the system on the random number in the operation process, and can also be used as a scheme reference for designing the true random number in other chip development or FPGA development, and FIG. 10 is a working flow of calling the true random number generator by the system.
In the embodiment, after the control circuit opens the clock gating signal and selects the random source, the true random number module is started, and after the module generates reset of a plurality of clock cycles, the random source circuit starts to work and outputs a random number; the module is flexible in design and needs to be flexibly designed according to application scenes.
By adopting the technical scheme disclosed by the invention, the following beneficial effects are obtained:
the invention provides a true random number generator of a pure digital circuit, which has the characteristics of simple circuit structure, easy realization, higher random number quality, uniform distribution, unpredictability, low power consumption and attack resistance, and has strong engineering reference and application values; the true random number generator can be used as a soft IP of a smart card chip for system calling so as to meet the requirement on random numbers in the system operation process, and can also be used as a scheme reference for designing true random numbers in other chip development or FPGA development.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and improvements can be made without departing from the principle of the present invention, and such modifications and improvements should also be considered within the scope of the present invention.
Claims (4)
1. A pure digital circuit true random number generator comprises an entropy source circuit, a sampling circuit and an output register circuit, wherein the sampling circuit is connected with the entropy source circuit; the method is characterized in that: the generator also comprises a post-processing circuit, the post-processing circuit is arranged between the sampling circuit and the output register circuit and respectively connected with the sampling circuit and the output register circuit, the post-processing circuit comprises a linear feedback shift register connected with the sampling circuit, a detection circuit connected with the linear feedback shift register and a random extraction circuit connected with the detection circuit, and the output register circuit is connected with the random extraction circuit to latch the output of the random extraction circuit;
the generator also comprises a random extractor circuit, wherein the random extractor circuit is connected with the detection circuit and is used for extracting the random number sequence sent to the detection circuit to obtain mbit random numbers, and m is the bit width of the random number sequence;
the entropy source circuit comprises a plurality of random source circuits, namely a first random source circuit based on a metastable state, a second random source circuit based on even ring collapse time and a third random source circuit based on ring oscillation jitter, wherein each random source circuit can provide a data input signal for the D end of the sampling circuit;
the first random source circuit comprises M SR latch units, wherein the SR latch units are arranged in parallel and carry out XOR operation, and the operation result is used as the output of the entropy source circuit; m is more than or equal to 128;
the second random source circuit comprises N inverters and two exclusive-OR gates which are sequentially connected end to end, and N/2 inverters are arranged between the two exclusive-OR gates; n is an even number;
the two exclusive-or gates are respectively a first exclusive-or gate and a second exclusive-or gate, and the second random source circuit is provided with two signal transmission paths which are respectively a first signal transmission path and a second signal transmission path; the first exclusive-or gate only allows the first signal transmission path to pass through, and the second exclusive-or gate only allows the second transmission path to pass through;
the third random source circuit comprises a plurality of ring oscillators, each ring oscillator is composed of an odd number of inverters, and an AND gate is arranged in each ring oscillator; the AND gates and the inverters in the same ring oscillator are sequentially connected end to end, the output end of the inverter at the most downstream in the signal transmission direction in the ring oscillator is connected with the input end of the AND gate, and the output end of the AND gate is connected with the input end of the inverter at the most upstream; and connecting the output ends of the ring oscillators with different lengths with the same third XOR gate in pairs for XOR processing, and then connecting the output ends of the third XOR gates with the fourth XOR gate.
2. The true random number generator of claim 1, wherein: the generator further comprises a control circuit, and the control circuit is respectively connected with the sampling circuit, the linear feedback shift register, the detection circuit, the random extraction circuit and the output register circuit.
3. The true random number generator of claim 2, wherein: the entropy source circuit is connected with the sampling circuit, and the sampling circuit uses a low-frequency sampling clock as a clock signal of a D end of the rising edge trigger sampling circuit; the output signal of the entropy source circuit is used as a data input signal of a D end of the sampling circuit, and is sampled at the rising edge of the sampling clock pulse, so that a true random number bit stream is obtained at a Q end of the sampling circuit.
4. The true random number generator of claim 1, wherein: the linear feedback shift register sends the random number sequence output by the linear feedback shift register to a detection circuit, and the random number sequence takes (8m) bit as a unit.
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| TWI811642B (en) * | 2021-03-08 | 2023-08-11 | 新唐科技股份有限公司 | Random-number generator circuit and random-number generation method |
| CN113377337B (en) * | 2021-07-07 | 2022-11-04 | 山东方寸微电子科技有限公司 | True random number generator and chip |
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